FireBridge: Cycle-Accurate Hardware + Firmware Co-Verification for Modern Accelerators
Fuente:
arXiv
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| Autori principali: | , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866914464507363328 |
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| author | Abarajithan, G Ma, Zhenghua Restuccia, Francesco Kastner, Ryan |
| author_facet | Abarajithan, G Ma, Zhenghua Restuccia, Francesco Kastner, Ryan |
| contents | Hardware-firmware integration is becoming a productivity bottleneck due to the increasing complexity of accelerators, characterized by intricate memory hierarchies and firmware-intensive execution. While numerous verification techniques focus on early-stage, approximate modeling of such systems to speed up initial development, developers still rely heavily on FPGA emulation to integrate firmware with RTL/HLS hardware, resulting in significant delays in debug iterations and time-to-market. We present a fast, cycle-accurate co-verification framework that bridges production firmware and RTL/gate-level hardware. FIREBRIDGE enables firmware debugging, profiling, and verification in seconds using standard simulators such as VCS, Vivado Xsim, or Xcelium, by compiling the firmware for x86 and bridging it with simulated subsystems via randomized memory bridges. Our approach provides off-chip data movement profiling, memory congestion emulation, and register-level protocol testing, which are critical for modern accelerator verification. We demonstrate a speedup of up to 50x in debug iteration over the conventional FPGA-based flow for system integration between RTL/HLS and production firmware on various types of accelerators, such as systolic arrays and CGRAs, while ensuring functional equivalence. FIREBRIDGE accelerates system integration by supporting robust co-verification of hardware and firmware, and promotes a structured, parallel development workflow tailored for teams building heterogeneous computing platforms.
Repository: https://github.com/abarajithan11/axis-systolic-array/tree/master/firebridge |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_25969 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | FireBridge: Cycle-Accurate Hardware + Firmware Co-Verification for Modern Accelerators Abarajithan, G Ma, Zhenghua Restuccia, Francesco Kastner, Ryan Hardware Architecture Hardware-firmware integration is becoming a productivity bottleneck due to the increasing complexity of accelerators, characterized by intricate memory hierarchies and firmware-intensive execution. While numerous verification techniques focus on early-stage, approximate modeling of such systems to speed up initial development, developers still rely heavily on FPGA emulation to integrate firmware with RTL/HLS hardware, resulting in significant delays in debug iterations and time-to-market. We present a fast, cycle-accurate co-verification framework that bridges production firmware and RTL/gate-level hardware. FIREBRIDGE enables firmware debugging, profiling, and verification in seconds using standard simulators such as VCS, Vivado Xsim, or Xcelium, by compiling the firmware for x86 and bridging it with simulated subsystems via randomized memory bridges. Our approach provides off-chip data movement profiling, memory congestion emulation, and register-level protocol testing, which are critical for modern accelerator verification. We demonstrate a speedup of up to 50x in debug iteration over the conventional FPGA-based flow for system integration between RTL/HLS and production firmware on various types of accelerators, such as systolic arrays and CGRAs, while ensuring functional equivalence. FIREBRIDGE accelerates system integration by supporting robust co-verification of hardware and firmware, and promotes a structured, parallel development workflow tailored for teams building heterogeneous computing platforms. Repository: https://github.com/abarajithan11/axis-systolic-array/tree/master/firebridge |
| title | FireBridge: Cycle-Accurate Hardware + Firmware Co-Verification for Modern Accelerators |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.25969 |