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| Main Authors: | , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2603.26016 |
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| _version_ | 1866915893530853376 |
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| author | Dong, Weirong Zhou, Kai Kong, Zhen Yang, Zhengke Cheng, Quan Li, Haoyuan Huang, Junkai Lan, Jun Li, Yida Hashimoto, Masanori Lin, Longyang |
| author_facet | Dong, Weirong Zhou, Kai Kong, Zhen Yang, Zhengke Cheng, Quan Li, Haoyuan Huang, Junkai Lan, Jun Li, Yida Hashimoto, Masanori Lin, Longyang |
| contents | RRAM-based in-memory computing (IMC) offers high energy efficiency but suffers from conductance drift that severely degrades long-term accuracy. Existing approaches including retraining, noise-aware training, and Batch Normalization (BN)-based calibration either require RRAM rewriting, demand large storage overhead, or rely on online correction. We propose VeRA+, a lightweight drift compensation framework that reuses shared projection matrices and introduces only two compact drift-specific vectors per drift level. A drift-aware scheduling algorithm offline-trains a small set of VeRA+ parameters and selects the appropriate set over time without any on-chip retraining or data replay. VeRA+ preserves up to 99.77% of the drift-free accuracy after ten years of simulated drift and reduces storage overhead by more than three orders of magnitude compared with BN-based calibration. To validate VeRA+ under realistic device behavior, we extract one-week drift statistics from measurements on our fabricated 1T1R RRAM devices and use them to simulate realistic drifted weights. Under these measured drift conditions, VeRA+ achieves accuracy close to the drift-free baseline, providing an efficient and practical solution for long-term drift resilience in RRAM-IMC. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_26016 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | VeRA+: Vector-Based Lightweight Digital Compensation for Drift-Resilient RRAM In-Memory Computing Dong, Weirong Zhou, Kai Kong, Zhen Yang, Zhengke Cheng, Quan Li, Haoyuan Huang, Junkai Lan, Jun Li, Yida Hashimoto, Masanori Lin, Longyang Hardware Architecture RRAM-based in-memory computing (IMC) offers high energy efficiency but suffers from conductance drift that severely degrades long-term accuracy. Existing approaches including retraining, noise-aware training, and Batch Normalization (BN)-based calibration either require RRAM rewriting, demand large storage overhead, or rely on online correction. We propose VeRA+, a lightweight drift compensation framework that reuses shared projection matrices and introduces only two compact drift-specific vectors per drift level. A drift-aware scheduling algorithm offline-trains a small set of VeRA+ parameters and selects the appropriate set over time without any on-chip retraining or data replay. VeRA+ preserves up to 99.77% of the drift-free accuracy after ten years of simulated drift and reduces storage overhead by more than three orders of magnitude compared with BN-based calibration. To validate VeRA+ under realistic device behavior, we extract one-week drift statistics from measurements on our fabricated 1T1R RRAM devices and use them to simulate realistic drifted weights. Under these measured drift conditions, VeRA+ achieves accuracy close to the drift-free baseline, providing an efficient and practical solution for long-term drift resilience in RRAM-IMC. |
| title | VeRA+: Vector-Based Lightweight Digital Compensation for Drift-Resilient RRAM In-Memory Computing |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.26016 |