Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System
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arXiv
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| Autores principales: | , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866911547939356672 |
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| author | Sullivan, Connor Rudy Mamandipoor, Amin Strickler, Cole Ridge Yun, Heechul |
| author_facet | Sullivan, Connor Rudy Mamandipoor, Amin Strickler, Cole Ridge Yun, Heechul |
| contents | Modern multicore system-on-chips (SoCs) share off-chip DRAM across cores, where bank-level interference can significantly degrade performance and threaten real-time guarantees. While prior work has focused on per-core bandwidth regulation, these approaches treat main memory as a monolithic resource and overlook DRAM's inherent bank-level parallelism.
We show that DRAM interference is fundamentally a bank-level phenomenon. We characterize the guaranteed bandwidth of modern DRAM, demonstrate that it remains effectively constant across generations, and show how this limitation can be exploited by single-bank attacks. These results highlight the need for bank-aware memory management for predictable and efficient real-time systems.
We design and implement a novel per-bank memory bandwidth regulator in an open-source RISC-V SoC and evaluate it using FireSim with both synthetic and real-world workloads. Our evaluation demonstrates that per-bank regulation effectively mitigates adversarial bank contention and achieves a 5.74x average throughput improvement for best-effort workloads over traditional bank-oblivious approaches while providing the same-level of performance isolation guarantees for real-time workloads. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_26054 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System Sullivan, Connor Rudy Mamandipoor, Amin Strickler, Cole Ridge Yun, Heechul Hardware Architecture Modern multicore system-on-chips (SoCs) share off-chip DRAM across cores, where bank-level interference can significantly degrade performance and threaten real-time guarantees. While prior work has focused on per-core bandwidth regulation, these approaches treat main memory as a monolithic resource and overlook DRAM's inherent bank-level parallelism. We show that DRAM interference is fundamentally a bank-level phenomenon. We characterize the guaranteed bandwidth of modern DRAM, demonstrate that it remains effectively constant across generations, and show how this limitation can be exploited by single-bank attacks. These results highlight the need for bank-aware memory management for predictable and efficient real-time systems. We design and implement a novel per-bank memory bandwidth regulator in an open-source RISC-V SoC and evaluate it using FireSim with both synthetic and real-world workloads. Our evaluation demonstrates that per-bank regulation effectively mitigates adversarial bank contention and achieves a 5.74x average throughput improvement for best-effort workloads over traditional bank-oblivious approaches while providing the same-level of performance isolation guarantees for real-time workloads. |
| title | Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.26054 |