IBEX: Internal Bandwidth-Efficient Compression Architecture for Scalable CXL Memory Expansion
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
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2026
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| _version_ | 1866912984929927168 |
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| author | Ko, Younghoon Park, Hyemin Lee, Hyuk-Jae Lee, Hyokeun |
| author_facet | Ko, Younghoon Park, Hyemin Lee, Hyuk-Jae Lee, Hyokeun |
| contents | As the memory channel count is confined by physical dimensions, memory expanders appear to be a promising approach to extending memory capacity and channels by augmenting the existing I/O interface (e.g., PCIe) with memory-semantic protocols like CXL. Unfortunately, the physical constraints of a computing system restrict scalable capacity expansion with memory expanders. In this work, we propose a block-level compression scheme for modern memory expanders, IBEX, to achieve larger effective memory capacity. Given the performance overhead associated with block-level compression algorithms (e.g., LZ77), IBEX employs a promotion-based approach: only cold data is compressed, whereas hot data remains uncompressed. Our key innovation is internal bandwidth-efficient block management that precisely identifies cold pages with minimal metadata access overhead. Still, the promotion-based approach poses several performance-related challenges at the design level. Therefore, we also propose a shadowed promotion scheme that temporarily postpones the deallocation of promoted data, thereby mitigating the performance penalty incurred by demotion (i.e., recompression). Furthermore, we optimize our compression scheme by compacting metadata and co-locating multiple target blocks for efficient bandwidth utilization. Consequently, IBEX achieves an average of 1.28x-1.40x speedups compared to the state-of-the-art promotion-based block-level approaches. We open-source IBEX at https://github.com/relacslab/ibex-ics26. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_26131 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | IBEX: Internal Bandwidth-Efficient Compression Architecture for Scalable CXL Memory Expansion Ko, Younghoon Park, Hyemin Lee, Hyuk-Jae Lee, Hyokeun Hardware Architecture As the memory channel count is confined by physical dimensions, memory expanders appear to be a promising approach to extending memory capacity and channels by augmenting the existing I/O interface (e.g., PCIe) with memory-semantic protocols like CXL. Unfortunately, the physical constraints of a computing system restrict scalable capacity expansion with memory expanders. In this work, we propose a block-level compression scheme for modern memory expanders, IBEX, to achieve larger effective memory capacity. Given the performance overhead associated with block-level compression algorithms (e.g., LZ77), IBEX employs a promotion-based approach: only cold data is compressed, whereas hot data remains uncompressed. Our key innovation is internal bandwidth-efficient block management that precisely identifies cold pages with minimal metadata access overhead. Still, the promotion-based approach poses several performance-related challenges at the design level. Therefore, we also propose a shadowed promotion scheme that temporarily postpones the deallocation of promoted data, thereby mitigating the performance penalty incurred by demotion (i.e., recompression). Furthermore, we optimize our compression scheme by compacting metadata and co-locating multiple target blocks for efficient bandwidth utilization. Consequently, IBEX achieves an average of 1.28x-1.40x speedups compared to the state-of-the-art promotion-based block-level approaches. We open-source IBEX at https://github.com/relacslab/ibex-ics26. |
| title | IBEX: Internal Bandwidth-Efficient Compression Architecture for Scalable CXL Memory Expansion |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.26131 |