Efficient CMOS Invertible Logic Using Stochastic Computing
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arXiv
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| Autores principales: | , , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866918414090502144 |
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| author | Smithson, Sean C. Onizawa, Naoya Meyer, Brett H. Gross, Warren J. Hanyu, Takahiro |
| author_facet | Smithson, Sean C. Onizawa, Naoya Meyer, Brett H. Gross, Warren J. Hanyu, Takahiro |
| contents | Invertible logic can operate in one of two modes: 1) a forward mode, in which inputs are presented and a single, correct output is produced, and 2) a reverse mode, in which the output is fixed and the inputs take on values consistent with the output. It is possible to create invertible logic using various Boltzmann machine configurations. Such systems have been shown to solve certain challenging problems quickly, such as factorization and combinatorial optimization. In this paper, we show that invertible logic can be implemented using simple spiking neural networks based on stochastic computing. We present a design methodology for invertible stochastic gates, which can be implemented using a small amount of CMOS hardware. We demonstrate that our design can not only correctly implement basic gates with invertible capability, but can also be extended to construct invertible stochastic adder and multiplier circuits. Experimental results are presented which demonstrate correct operation of synthesizable invertible circuitry performing both multiplication and factorization, along with fabricated ASIC measurement results for an invertible multiplier circuit. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_27030 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Efficient CMOS Invertible Logic Using Stochastic Computing Smithson, Sean C. Onizawa, Naoya Meyer, Brett H. Gross, Warren J. Hanyu, Takahiro Hardware Architecture Invertible logic can operate in one of two modes: 1) a forward mode, in which inputs are presented and a single, correct output is produced, and 2) a reverse mode, in which the output is fixed and the inputs take on values consistent with the output. It is possible to create invertible logic using various Boltzmann machine configurations. Such systems have been shown to solve certain challenging problems quickly, such as factorization and combinatorial optimization. In this paper, we show that invertible logic can be implemented using simple spiking neural networks based on stochastic computing. We present a design methodology for invertible stochastic gates, which can be implemented using a small amount of CMOS hardware. We demonstrate that our design can not only correctly implement basic gates with invertible capability, but can also be extended to construct invertible stochastic adder and multiplier circuits. Experimental results are presented which demonstrate correct operation of synthesizable invertible circuitry performing both multiplication and factorization, along with fabricated ASIC measurement results for an invertible multiplier circuit. |
| title | Efficient CMOS Invertible Logic Using Stochastic Computing |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.27030 |