RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning
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arXiv
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| Auteurs principaux: | , , , , , , , , |
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| Format: | Preprint |
| Publié: |
2026
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| _version_ | 1866908919490674688 |
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| author | Zhang, Xinyu Chao, Zhiteng Wang, Yonghao Sun, Bin Ma, Tianyun Yang, Tianmeng Mu, Jianan Ye, Jing Justin Li, Huawei |
| author_facet | Zhang, Xinyu Chao, Zhiteng Wang, Yonghao Sun, Bin Ma, Tianyun Yang, Tianmeng Mu, Jianan Ye, Jing Justin Li, Huawei |
| contents | Register Transfer Level (RTL) design translates high-level specifications into hardware using HDLs such as Verilog. Although LLM-based RTL generation is promising, the scarcity of functionally verifiable high-quality data limits both accuracy and diversity. Existing post-training typically produces a single HDL implementation per specification, lacking awareness of RTL variations needed for different design goals. We propose RTLSeek, a post-training paradigm that applies rule-based Diversity-Oriented Reinforcement Learning to improve RTL correctness and diversity. Our Diversity-Centric Multi-Objective Reward Scheduling integrates expert knowledge with EDA feedback, and a three-stage framework maximizes the utility of limited data. Experiments on the RTLLM benchmark show that RTLSeek surpasses prior methods, with ablation results confirming that encouraging broader design-space exploration improves RTL quality and achieves the principle of "the more generated, the better results." Implementation framework, including the dataset, source code, and model weights, is shown at https://anonymous.4open.science/r/DAC2026ID71-ACB4/. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_27630 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning Zhang, Xinyu Chao, Zhiteng Wang, Yonghao Sun, Bin Ma, Tianyun Yang, Tianmeng Mu, Jianan Ye, Jing Justin Li, Huawei Hardware Architecture Machine Learning Register Transfer Level (RTL) design translates high-level specifications into hardware using HDLs such as Verilog. Although LLM-based RTL generation is promising, the scarcity of functionally verifiable high-quality data limits both accuracy and diversity. Existing post-training typically produces a single HDL implementation per specification, lacking awareness of RTL variations needed for different design goals. We propose RTLSeek, a post-training paradigm that applies rule-based Diversity-Oriented Reinforcement Learning to improve RTL correctness and diversity. Our Diversity-Centric Multi-Objective Reward Scheduling integrates expert knowledge with EDA feedback, and a three-stage framework maximizes the utility of limited data. Experiments on the RTLLM benchmark show that RTLSeek surpasses prior methods, with ablation results confirming that encouraging broader design-space exploration improves RTL quality and achieves the principle of "the more generated, the better results." Implementation framework, including the dataset, source code, and model weights, is shown at https://anonymous.4open.science/r/DAC2026ID71-ACB4/. |
| title | RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning |
| topic | Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2603.27630 |