AXON: An Automated Netlist Optimization Framework for High-Speed Adders
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arXiv
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| Autores principales: | , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| Acceso en línea: | |
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| _version_ | 1866918416930045952 |
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| author | Yang, Tiantian Ren, Xuanle Wan, Qingdian Meng, Qi |
| author_facet | Yang, Tiantian Ren, Xuanle Wan, Qingdian Meng, Qi |
| contents | Adders are fundamental building blocks in modern digital systems, and their performance, power, and area (PPA) directly impact system efficiency. Contemporary adders typically use parallel-prefix architectures with established PPA trade-offs, but these often fail to deliver globally optimal PPA for specific design goals. Prior work lacks netlist-/cell-level awareness, and general synthesis heuristics are not adder-specific, resulting in suboptimal PPA. To address this, we propose AXON, an automated netlist optimization framework for adders. It performs design space exploration from architectural to netlist level, integrating prefix topology search with standard-cell-aware mapping via a hierarchical approach to quickly converge to near-optimal PPA solutions. We also introduce a hybrid ultra-high-speed adder combining parallel-prefix and Ling architectures to shorten the critical path. Experiments on TSMC 28nm library show AXON improves delay, area-delay product, and energy-delay product by up to 10.3%, 12.6%, and 32.1% respectively, compared to commercial synthesis tools. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_28184 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | AXON: An Automated Netlist Optimization Framework for High-Speed Adders Yang, Tiantian Ren, Xuanle Wan, Qingdian Meng, Qi Hardware Architecture Adders are fundamental building blocks in modern digital systems, and their performance, power, and area (PPA) directly impact system efficiency. Contemporary adders typically use parallel-prefix architectures with established PPA trade-offs, but these often fail to deliver globally optimal PPA for specific design goals. Prior work lacks netlist-/cell-level awareness, and general synthesis heuristics are not adder-specific, resulting in suboptimal PPA. To address this, we propose AXON, an automated netlist optimization framework for adders. It performs design space exploration from architectural to netlist level, integrating prefix topology search with standard-cell-aware mapping via a hierarchical approach to quickly converge to near-optimal PPA solutions. We also introduce a hybrid ultra-high-speed adder combining parallel-prefix and Ling architectures to shorten the critical path. Experiments on TSMC 28nm library show AXON improves delay, area-delay product, and energy-delay product by up to 10.3%, 12.6%, and 32.1% respectively, compared to commercial synthesis tools. |
| title | AXON: An Automated Netlist Optimization Framework for High-Speed Adders |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.28184 |