Cover Image

AXON: An Automated Netlist Optimization Framework for High-Speed Adders

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Yang, Tiantian, Ren, Xuanle, Wan, Qingdian, Meng, Qi
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimization
by: Zuo, Dongsheng, et al.
Published: (2025)

Online Alignment and Addition in Multi-Term Floating-Point Adders
by: Alexandridis, Kosmas, et al.
Published: (2024)

Floating Point HUB Adder for RISC-V Sargantana Processor
by: Bandera, Gerardo, et al.
Published: (2024)

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
by: Bhandari, Jitendra, et al.
Published: (2024)

Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization
by: Ren, Yi, et al.
Published: (2025)

Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic
by: Balasubramanian, Padmanabhan, et al.
Published: (2024)

Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
by: Pun, Junius, et al.
Published: (2025)

Aligning Netlist to Source Code using SynAlign
by: Garg, Sakshi, et al.
Published: (2025)

There and Back Again: A Netlist's Tale with Much Egraphin'
by: Smith, Gus Henry, et al.
Published: (2024)

HALOC-AxA: An Area/-Energy-Efficient Approximate Adder for Image Processing Application
by: Ziad, Hasnain A., et al.
Published: (2025)

FPGA-Based Multiplier with a New Approximate Full Adder for Error-Resilient Applications
by: Ranjbar, Ali, et al.
Published: (2025)

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
by: Li, Runkai, et al.
Published: (2025)

Novel Optimized Designs of Modulo $2n+1$ Adder for Quantum Computing
by: Gaur, Bhaskar, et al.
Published: (2024)

DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators
by: Xue, Chenhao, et al.
Published: (2025)

DE-HNN: An effective neural model for Circuit Netlist representation
by: Luo, Zhishang, et al.
Published: (2024)

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
by: Saravanan, Raghul, et al.
Published: (2025)

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
by: Li, Wenkai, et al.
Published: (2025)

Semicustom Frontend VLSI Design and Analysis of a 32-bit Brent-Kung Adder in Cadence Suite
by: Singh, Yashvardhan
Published: (2025)

EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
by: Zhu, Jiaying, et al.
Published: (2026)

Novel Efficient Scalable QCA XOR and Full Adder Designs
by: Safaiezadeh, Behrouz, et al.
Published: (2023)

ArtNet: Hierarchical Clustering-Based Artificial Netlist Generator for ML and DTCO Application
by: Kang, Andrew B. Kahng. Seokhyeong, et al.
Published: (2025)

VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
by: Qi, Haomin, et al.
Published: (2025)

FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
by: Abi-Karam, Stefan, et al.
Published: (2025)

Configurable Multi-Port Memory Architecture for High-Speed Data Communication
by: Dhakad, Narendra Singh, et al.
Published: (2024)

Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing
by: Gaur, Bhaskar, et al.
Published: (2024)

Automated SVA Generation with LLMs
by: Fu, Lik Tung, et al.
Published: (2026)

Design of a Reformed Array Logic Binary Multiplier for High-Speed Computations
by: Mohammad, Sakib, et al.
Published: (2024)

Schemato -- An LLM for Netlist-to-Schematic Conversion
by: Matsuo, Ryoga, et al.
Published: (2024)

AGON: Automated Design Framework for Customizing Processors from ISA Documents
by: Li, Chongxiao, et al.
Published: (2024)

PrefixGPT: Prefix Adder Optimization by a Generative Pre-trained Transformer
by: Ding, Ruogu, et al.
Published: (2025)

CODO: An Automated Compiler for Comprehensive Dataflow Optimization
by: Zhang, Weichuang, et al.
Published: (2026)

CellE: Automated Standard Cell Library Extension via Equality Saturation
by: Ren, Yi, et al.
Published: (2026)

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
by: Fang, Wenji, et al.
Published: (2025)

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
by: Fang, Wenji, et al.
Published: (2025)

A Logarithmic Depth Quantum Carry-Lookahead Modulo $(2^n-1)$ Adder
by: Gaur, Bhaskar, et al.
Published: (2024)

Combined power management and congestion control in High-Speed Ethernet-based Networks for Supercomputers and Data Centers
by: de la Rosa, Miguel Sánchez, et al.
Published: (2025)

CREATE: Cross-Layer Resilience Characterization and Optimization for Efficient yet Reliable Embodied AI Systems
by: Xie, Tong, et al.
Published: (2026)

UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators
by: Zuo, Dongsheng, et al.
Published: (2024)

Extracting TCPIP Headers at High Speed for the Anonymized Network Traffic Graph Challenge
by: Han, Zhaoyang, et al.
Published: (2024)

RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device
by: Fu, Siqing, et al.
Published: (2023)