Loop Control Management in Tightly Coupled Processor Arrays (TCPAs)
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arXiv
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| Autores principales: | , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866912989099065344 |
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| author | Walter, Dominik Hannig, Frank Teich, Jürgen |
| author_facet | Walter, Dominik Hannig, Frank Teich, Jürgen |
| contents | Multidimensional loop kernels often suffer from control overhead that can dominate execution time on parallel loop accelerators. Tightly Coupled Processor Arrays (TCPAs) offload loop control to a global controller (GC), but existing approaches still require hundreds of control signals. We propose a method to derive and aggressively reduce these control conditions from a polyhedral representation of the iteration space, achieving reductions of 15x to 45x in control signals across several benchmarks. We introduce a lightweight GC architecture that evaluates conditions as unions of polyhedra using bounded evaluation units, requiring hardware comparable to a single processing element. Control signals are distributed throughout the array with a minimal number of delay elements resulting in zero-overhead loop control. Our evaluation on PolyBench kernels shows that the entire control flow requires < 10 % of the total array resources. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_28645 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Loop Control Management in Tightly Coupled Processor Arrays (TCPAs) Walter, Dominik Hannig, Frank Teich, Jürgen Hardware Architecture Multidimensional loop kernels often suffer from control overhead that can dominate execution time on parallel loop accelerators. Tightly Coupled Processor Arrays (TCPAs) offload loop control to a global controller (GC), but existing approaches still require hundreds of control signals. We propose a method to derive and aggressively reduce these control conditions from a polyhedral representation of the iteration space, achieving reductions of 15x to 45x in control signals across several benchmarks. We introduce a lightweight GC architecture that evaluates conditions as unions of polyhedra using bounded evaluation units, requiring hardware comparable to a single processing element. Control signals are distributed throughout the array with a minimal number of delay elements resulting in zero-overhead loop control. Our evaluation on PolyBench kernels shows that the entire control flow requires < 10 % of the total array resources. |
| title | Loop Control Management in Tightly Coupled Processor Arrays (TCPAs) |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.28645 |