Cover Image

Loop Control Management in Tightly Coupled Processor Arrays (TCPAs)

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Walter, Dominik, Hannig, Frank, Teich, Jürgen
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs
by: Walter, Dominik, et al.
Published: (2025)

Symbolic Polyhedral-Based Energy Analysis for Nested Loop Programs
by: Nirmala, Avinash Mahesh, et al.
Published: (2026)

Evaluation of CGRA Toolchains
by: Walter, Dominik, et al.
Published: (2025)

Co-Design of CNN Accelerators for TinyML using Approximate Matrix Decomposition
by: Morales, José Juan Hernández, et al.
Published: (2026)

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
by: Sabih, Muhammad, et al.
Published: (2025)

Image processing Application Development on Software Configurable Processor Array
by: Prabhu, Ganesh, et al.
Published: (2025)

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
by: Ottaviano, Alessandro, et al.
Published: (2023)

MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-core Processor
by: Sui, Bingcai, et al.
Published: (2024)

relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
by: Rogenmoser, Michael, et al.
Published: (2025)

Large Processor Chip Model
by: Chang, Kaiyan, et al.
Published: (2025)

Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor
by: Kirschner, Maximilian, et al.
Published: (2024)

SAMIPS: A Synthesised Asynchronous Processor
by: Zhang, Qianyi, et al.
Published: (2024)

Banked Memories for Soft SIMT Processors
by: Langhammer, Martin, et al.
Published: (2025)

MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
by: Kirschner, Maximilian, et al.
Published: (2025)

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
by: Rogenmoser, Michael, et al.
Published: (2024)

A 950 MHz SIMT Soft Processor
by: Langhammer, Martin, et al.
Published: (2025)

Hypervisor Extension for a RISC-V Processor
by: Gauchola, Jaume, et al.
Published: (2024)

Implementation of Compute Intensive Algorithms on Software Configurable Processor
by: Ganesha, et al.
Published: (2025)

Duet: Creating Harmony between Processors and Embedded FPGAs
by: Li, Ang, et al.
Published: (2023)

Web-Based Simulator of Superscalar RISC-V Processors
by: Jaros, Jiri, et al.
Published: (2024)

Neuromorphic Processor Employing FPGA Technology with Universal Interconnections
by: Harlikar, Pracheta, et al.
Published: (2025)

Closed-Loop Environmental Control System on Embedded Systems
by: Goswami, Irisha M., et al.
Published: (2026)

Functional ISS-Driven Verification of Superscalar RISC-V Processors
by: Galimberti, Andrea, et al.
Published: (2024)

Floating Point HUB Adder for RISC-V Sargantana Processor
by: Bandera, Gerardo, et al.
Published: (2024)

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
by: Rezunov, Evgenii, et al.
Published: (2025)

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
by: Zhong, Yang, et al.
Published: (2025)

AGON: Automated Design Framework for Customizing Processors from ISA Documents
by: Li, Chongxiao, et al.
Published: (2024)

On the Impact of ISA Extension on Energy Consumption of I-Cache in Extensible Processors
by: Behboudi, Noushin, et al.
Published: (2024)

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
by: Titopoulos, Vasileios, et al.
Published: (2025)

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
by: Papadopoulos, Nikolaos-Charalampos, et al.
Published: (2024)

TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads
by: Purayil, Navaneeth Kunhi, et al.
Published: (2025)

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025)

Systolic Array Acceleration of Diagonal-Optimized Sparse-Sparse Matrix Multiplication for Efficient Quantum Simulation
by: Su, Yuchao, et al.
Published: (2025)

TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks
by: Bertuletti, Marco, et al.
Published: (2026)

LPU: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference
by: Moon, Seungjae, et al.
Published: (2024)

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
by: Colagrande, Luca, et al.
Published: (2025)

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
by: McDougall, Ian, et al.
Published: (2025)

MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
by: You, Dean, et al.
Published: (2025)

FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation
by: Meng, Chengzhen, et al.
Published: (2025)

Diba: A Re-configurable Stream Processor
by: Najafi, Mohammadreza, et al.
Published: (2023)