CXLRAMSim v1.0: System-Level Exploration of CXL Memory Expander Cards
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arXiv
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| Auteurs principaux: | , , |
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| Format: | Preprint |
| Publié: |
2026
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| _version_ | 1866914434279014400 |
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| author | Pathak, Karan Atienza, David Zapater, Marina |
| author_facet | Pathak, Karan Atienza, David Zapater, Marina |
| contents | The growing demands in the training and inference of Large Language Models (LLMs) are accelerating the adoption of scale-up systems that extend server shared memory through the use of Compute Express Link (CXL)-based load/store interconnects. Accurate full-system simulation of such architectures remains challenging, as existing tools (all very recent) rely on simplified or non-compliant architectural models, impacting accuracy and usability. We present CXLRAMSim, the first gem5-integrated, full-system simulator that models CXL devices at their correct position on the I/O bus, enabling the use of unmodified Linux kernels and software stack, realistic latency-bandwidth behavior and true interleaving with system DRAM. Our approach provides high-fidelity CXL.mem characterization and captures key challenges such as cache pollution when accessing CXL memory. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_29483 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | CXLRAMSim v1.0: System-Level Exploration of CXL Memory Expander Cards Pathak, Karan Atienza, David Zapater, Marina Hardware Architecture Emerging Technologies The growing demands in the training and inference of Large Language Models (LLMs) are accelerating the adoption of scale-up systems that extend server shared memory through the use of Compute Express Link (CXL)-based load/store interconnects. Accurate full-system simulation of such architectures remains challenging, as existing tools (all very recent) rely on simplified or non-compliant architectural models, impacting accuracy and usability. We present CXLRAMSim, the first gem5-integrated, full-system simulator that models CXL devices at their correct position on the I/O bus, enabling the use of unmodified Linux kernels and software stack, realistic latency-bandwidth behavior and true interleaving with system DRAM. Our approach provides high-fidelity CXL.mem characterization and captures key challenges such as cache pollution when accessing CXL memory. |
| title | CXLRAMSim v1.0: System-Level Exploration of CXL Memory Expander Cards |
| topic | Hardware Architecture Emerging Technologies |
| url | https://arxiv.org/abs/2603.29483 |