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| Main Authors: | , , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2604.02811 |
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| _version_ | 1866917409291501568 |
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| author | Fu, Lik Tung Zhou, Jie Ren, Shaokai Zhang, Mengli Xiong, Jia Jiang, Hugo Guan, Nan Wang, Xi Yang, Jun |
| author_facet | Fu, Lik Tung Zhou, Jie Ren, Shaokai Zhang, Mengli Xiong, Jia Jiang, Hugo Guan, Nan Wang, Xi Yang, Jun |
| contents | Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced simulation-based debugging. However, manual SVA authoring is labor-intensive and error-prone. While Large Language Models (LLMs) show promise, their direct deployment is hindered by low functional accuracy and a severe scarcity of domain-specific data. To address these challenges, we introduce ChatSVA, an end-to-end SVA generation system built upon a multi-agent framework. At its core, the AgentBridge platform enables this multi-agent approach by systematically generating high-purity datasets, overcoming the data scarcity inherent to few-shot scenarios. Evaluated on 24 RTL designs, ChatSVA achieves 98.66% syntax and 96.12% functional pass rates, generating 139.5 SVAs per design with 82.50% function coverage. This represents a 33.3 percentage point improvement in functional correctness and an over 11x enhancement in function coverage compared to the previous state-of-the-art (SOTA). ChatSVA not only sets a new SOTA in automated SVA generation but also establishes a robust framework for solving long-chain reasoning problems in few-shot, domain-specific scenarios. An online service has been publicly released at https://www.nctieda.com/CHATDV.html. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_02811 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs Fu, Lik Tung Zhou, Jie Ren, Shaokai Zhang, Mengli Xiong, Jia Jiang, Hugo Guan, Nan Wang, Xi Yang, Jun Hardware Architecture Artificial Intelligence Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced simulation-based debugging. However, manual SVA authoring is labor-intensive and error-prone. While Large Language Models (LLMs) show promise, their direct deployment is hindered by low functional accuracy and a severe scarcity of domain-specific data. To address these challenges, we introduce ChatSVA, an end-to-end SVA generation system built upon a multi-agent framework. At its core, the AgentBridge platform enables this multi-agent approach by systematically generating high-purity datasets, overcoming the data scarcity inherent to few-shot scenarios. Evaluated on 24 RTL designs, ChatSVA achieves 98.66% syntax and 96.12% functional pass rates, generating 139.5 SVAs per design with 82.50% function coverage. This represents a 33.3 percentage point improvement in functional correctness and an over 11x enhancement in function coverage compared to the previous state-of-the-art (SOTA). ChatSVA not only sets a new SOTA in automated SVA generation but also establishes a robust framework for solving long-chain reasoning problems in few-shot, domain-specific scenarios. An online service has been publicly released at https://www.nctieda.com/CHATDV.html. |
| title | ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2604.02811 |