Style de citation APA (7e éd.)

Bao, X., & Chitnis, D. (2026). EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring.

Style de citation Chicago (17e éd.)

Bao, Xuanhao, et Danial Chitnis. EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring. 2026.

Style de citation MLA (9e éd.)

Bao, Xuanhao, et Danial Chitnis. EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring. 2026.

Attention : ces citations peuvent ne pas être correctes à 100%.