Cover Image

EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Bao, Xuanhao, Chitnis, Danial
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

EEsizer: LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit
by: Liu, Chang, et al.
Published: (2025)

LLM-based AI Agent for Sizing of Analog and Mixed Signal Circuit
by: Liu, Chang, et al.
Published: (2025)

CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations
by: Chen, Xiaoming
Published: (2024)

High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms
by: Wang, Hao, et al.
Published: (2024)

FsimNNs: An Open-Source Graph Neural Network Platform for SEU Simulation-based Fault Injection
by: Lu, Li, et al.
Published: (2025)

AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding
by: Kim, Seungmin, et al.
Published: (2026)

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
by: Emami, Mahyar, et al.
Published: (2023)

Human-AI Interaction: Evaluating LLM Reasoning on Digital Logic Circuit included Graph Problems, in terms of creativity in design and analysis
by: Thota, Yogeswar Reddy, et al.
Published: (2026)

Linear Complexity Fermionic Simulation on Quantum Devices with Hardware Connectivity Constraints
by: Gao, Xiangyu, et al.
Published: (2026)

Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures
by: Tang, Ruibai, et al.
Published: (2025)

SimulatorCoder: DNN Accelerator Simulator Code Generation and Optimization via Large Language Models
by: Xia, Yuhuan, et al.
Published: (2026)

GUST: Graph Edge-Coloring Utilization for Accelerating Sparse Matrix Vector Multiplication
by: Gerami, Armin, et al.
Published: (2024)

Circuit Diagram Retrieval Based on Hierarchical Circuit Graph Representation
by: Gao, Ming, et al.
Published: (2025)

GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
by: Fang, Wenji, et al.
Published: (2025)

Modular SAIL: dream or reality?
by: Kourzanov, Petr, et al.
Published: (2025)

RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule
by: Tang, Jiaping, et al.
Published: (2025)

SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm
by: Liu, Meng, et al.
Published: (2024)

ACALSim: A Scalable Parallel Simulation Framework for High-Performance System Design Space Exploration
by: Lin, Wei-Fen, et al.
Published: (2026)

CPPL: A Circuit Prompt Programming Language
by: Yin, Shuo, et al.
Published: (2026)

JugglePAC: A Pipelined Accumulation Circuit
by: Houraniah, Ahmad, et al.
Published: (2023)

Computing-In-Memory Aware Model Adaption For Edge Devices
by: Lin, Ming-Han, et al.
Published: (2025)

GraCo -- A Graph Composer for Integrated Circuits
by: Uhlich, Stefan, et al.
Published: (2024)

AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking
by: Hu, Guangyu, et al.
Published: (2026)

IMMSched: Interruptible Multi-DNN Scheduling via Parallel Multi-Particle Optimizing Subgraph Isomorphism
by: Zhao, Boran, et al.
Published: (2026)

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
by: Sun, Jialin, et al.
Published: (2025)

A Review of SRAM-based Compute-in-Memory Circuits
by: Yoshioka, Kentaro, et al.
Published: (2024)

Advanced Printed Sensors for Environmental Applications: A Path Towards Sustainable Monitoring Solutions
by: Papanikolaou, Nikolaos, et al.
Published: (2025)

Further Evaluations of a Didactic CPU Visual Simulator (CPUVSIM)
by: Cortinovis, Renato, et al.
Published: (2024)

Modulo-$(2^{2n}+1)$ Arithmetic via Two Parallel n-bit Residue Channels
by: Jaberipur, Ghassem, et al.
Published: (2024)

Modeling and Simulating Emerging Memory Technologies: A Tutorial
by: Chen, Yun-Chih, et al.
Published: (2025)

DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits
by: Ardakani, Arash, et al.
Published: (2025)

ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits
by: Zhang, Wenlun, et al.
Published: (2024)

DEFA: Efficient Deformable Attention Acceleration via Pruning-Assisted Grid-Sampling and Multi-Scale Parallel Processing
by: Xu, Yansong, et al.
Published: (2024)

BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning
by: Miao, Mingkai, et al.
Published: (2025)

Recurrent CircuitSAT Sampling for Sequential Circuits
by: Ardakani, Arash, et al.
Published: (2025)

ViPSN 2.0: A Reconfigurable Battery-free IoT Platform for Vibration Energy Harvesting
by: Li, Xin, et al.
Published: (2025)

SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
by: Brignone, Giovanni, et al.
Published: (2024)

MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator
by: Wang, Cong, et al.
Published: (2024)

DaPPA: A Data-Parallel Programming Framework for Processing-in-Memory Architectures
by: Oliveira, Geraldo F., et al.
Published: (2023)