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| Main Authors: | , , |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2604.04015 |
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| _version_ | 1866910104888016896 |
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| author | Yang, Hongbin Zhang, Huanle Pan, Runyu |
| author_facet | Yang, Hongbin Zhang, Huanle Pan, Runyu |
| contents | The growing complexity of real-time embedded systems demands strong isolation of software components into separate protection domains to reduce attack surfaces and limit fault propagation. However, application-supplied device interrupt handlers -- even untrusted -- have to remain in the kernel to minimize interrupt latency, undermining security and burdening manual certifications. Current hardware extensions accelerate interrupts only when the target protection domain is scheduled by the kernel; consequently, they are limited to improving average-case performance but not worst-case latency, and do not meet the requirements of critical real-time applications such as autonomous vehicles or robots.
To overcome this limitation, we propose a novel hardware extension that enables direct, deterministic switching to the appropriate protection domain upon user-level interrupt arrival -- without kernel intervention -- even when that domain is dormant. Our hardware extension reduces worst-case latency by more than 50x with a 19% increase in core area (2% of total die area) and 4.1% increase in dynamic power. To the best of our knowledge, this is the first integrated mechanism to guarantee user-level interrupt delivery with a nanosecond-scale yet bounded worst-case latency. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_04015 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Enabling Deterministic User-Level Interrupts in Real-Time Processors via Hardware Extension Yang, Hongbin Zhang, Huanle Pan, Runyu Cryptography and Security Hardware Architecture The growing complexity of real-time embedded systems demands strong isolation of software components into separate protection domains to reduce attack surfaces and limit fault propagation. However, application-supplied device interrupt handlers -- even untrusted -- have to remain in the kernel to minimize interrupt latency, undermining security and burdening manual certifications. Current hardware extensions accelerate interrupts only when the target protection domain is scheduled by the kernel; consequently, they are limited to improving average-case performance but not worst-case latency, and do not meet the requirements of critical real-time applications such as autonomous vehicles or robots. To overcome this limitation, we propose a novel hardware extension that enables direct, deterministic switching to the appropriate protection domain upon user-level interrupt arrival -- without kernel intervention -- even when that domain is dormant. Our hardware extension reduces worst-case latency by more than 50x with a 19% increase in core area (2% of total die area) and 4.1% increase in dynamic power. To the best of our knowledge, this is the first integrated mechanism to guarantee user-level interrupt delivery with a nanosecond-scale yet bounded worst-case latency. |
| title | Enabling Deterministic User-Level Interrupts in Real-Time Processors via Hardware Extension |
| topic | Cryptography and Security Hardware Architecture |
| url | https://arxiv.org/abs/2604.04015 |