DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration
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arXiv
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| Format: | Preprint |
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2026
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| _version_ | 1866910115056058368 |
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| author | Kumar, Shubham Sharma, Vijay Pratap Neema, Vaibhav Vishvakarma, Santosh Kumar |
| author_facet | Kumar, Shubham Sharma, Vijay Pratap Neema, Vaibhav Vishvakarma, Santosh Kumar |
| contents | The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a dual-precision floating-point MAC processing element supporting FP8 (E4M3, E5M2) and FP4 (2 x E2M1, 2 x E1M2) formats, specifically optimized for low-power and high-throughput AI workloads. The proposed architecture employs a novel bit-partitioning technique that enables a single 4-bit unit multiplier to operate either as a standard 4 x 4 multiplier for FP8 or as two parallel 2 x 2 multipliers for 2-bit operands, achieving maximum hardware utilization without duplicating logic. Implemented in 28 nm technology, the proposed PE achieves an operating frequency of 1.94 GHz with an area of 0.00396 mm^2 and power consumption of 2.13 mW, resulting in up to 60.4% area reduction and 86.6% power savings compared to state-of-the-art designs, making it well suited for energy-constrained AI inference and mixed-precision computing applications when deployed within larger accelerator architectures. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2604_04507 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration Kumar, Shubham Sharma, Vijay Pratap Neema, Vaibhav Vishvakarma, Santosh Kumar Hardware Architecture Robotics Audio and Speech Processing Image and Video Processing The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a dual-precision floating-point MAC processing element supporting FP8 (E4M3, E5M2) and FP4 (2 x E2M1, 2 x E1M2) formats, specifically optimized for low-power and high-throughput AI workloads. The proposed architecture employs a novel bit-partitioning technique that enables a single 4-bit unit multiplier to operate either as a standard 4 x 4 multiplier for FP8 or as two parallel 2 x 2 multipliers for 2-bit operands, achieving maximum hardware utilization without duplicating logic. Implemented in 28 nm technology, the proposed PE achieves an operating frequency of 1.94 GHz with an area of 0.00396 mm^2 and power consumption of 2.13 mW, resulting in up to 60.4% area reduction and 86.6% power savings compared to state-of-the-art designs, making it well suited for energy-constrained AI inference and mixed-precision computing applications when deployed within larger accelerator architectures. |
| title | DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration |
| topic | Hardware Architecture Robotics Audio and Speech Processing Image and Video Processing |
| url | https://arxiv.org/abs/2604.04507 |