Saved in:
| Main Author: | Olsen, Eric B. |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2604.04796 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Mirage: An RNS-Based Photonic Accelerator for DNN Training
by: Demirkiran, Cansu, et al.
Published: (2023)
by: Demirkiran, Cansu, et al.
Published: (2023)
Memory-Guided Unified Hardware Accelerator for Mixed-Precision Scientific Computing
by: Wang, Chuanzhen, et al.
Published: (2026)
by: Wang, Chuanzhen, et al.
Published: (2026)
Rescaling-Aware Training for Efficient Deployment of Deep Learning Models on Full-Integer Hardware
by: Mueller, Lion, et al.
Published: (2025)
by: Mueller, Lion, et al.
Published: (2025)
SoftmAP: Software-Hardware Co-design for Integer-Only Softmax on Associative Processors
by: Rakka, Mariam, et al.
Published: (2024)
by: Rakka, Mariam, et al.
Published: (2024)
Digit-Recurrence Posit Division
by: Murillo, Raul, et al.
Published: (2025)
by: Murillo, Raul, et al.
Published: (2025)
Residue Number System (RNS) based Distributed Quantum Addition
by: Gaur, Bhaskar, et al.
Published: (2024)
by: Gaur, Bhaskar, et al.
Published: (2024)
Efficient Multi-Cycle Folded Integer Multipliers
by: Houraniah, Ahmad, et al.
Published: (2023)
by: Houraniah, Ahmad, et al.
Published: (2023)
SkyByte: Architecting an Efficient Memory-Semantic CXL-based SSD with OS and Hardware Co-design
by: Zhang, Haoyang, et al.
Published: (2025)
by: Zhang, Haoyang, et al.
Published: (2025)
Sustainable Hardware Specialization
by: Dangi, Pranav, et al.
Published: (2024)
by: Dangi, Pranav, et al.
Published: (2024)
Analyzing and Improving Hardware Modeling of Accel-Sim
by: Huerta, Rodrigo, et al.
Published: (2024)
by: Huerta, Rodrigo, et al.
Published: (2024)
Hardware and software build flow with SoCMake
by: Pejašinović, Risto, et al.
Published: (2025)
by: Pejašinović, Risto, et al.
Published: (2025)
QED: Scalable Verification of Hardware Memory Consistency
by: Ravi, Gokulan, et al.
Published: (2024)
by: Ravi, Gokulan, et al.
Published: (2024)
NeuroVM: Dynamic Neuromorphic Hardware Virtualization
by: Isik, Murat, et al.
Published: (2024)
by: Isik, Murat, et al.
Published: (2024)
In-Memory Computing Architecture for Efficient Hardware Security
by: Ajmi, Hala, et al.
Published: (2024)
by: Ajmi, Hala, et al.
Published: (2024)
Closing the Gap Between Float and Posit Hardware Efficiency
by: Jonnalagadda, Aditya Anirudh, et al.
Published: (2026)
by: Jonnalagadda, Aditya Anirudh, et al.
Published: (2026)
Hardware-Aware DNN Compression for Homogeneous Edge Devices
by: Zhang, Kunlong, et al.
Published: (2025)
by: Zhang, Kunlong, et al.
Published: (2025)
Look-Up Table based Neural Network Hardware
by: Sen, Ovishake, et al.
Published: (2024)
by: Sen, Ovishake, et al.
Published: (2024)
SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators
by: Umuroglu, Yaman, et al.
Published: (2025)
by: Umuroglu, Yaman, et al.
Published: (2025)
Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration
by: Shahawy, Mohamed, et al.
Published: (2025)
by: Shahawy, Mohamed, et al.
Published: (2025)
HLStrans: Dataset for C-to-HLS Hardware Code Synthesis
by: Zou, Qingyun, et al.
Published: (2025)
by: Zou, Qingyun, et al.
Published: (2025)
A Power-Efficient Hardware Implementation of L-Mul
by: Chen, Ruiqi, et al.
Published: (2024)
by: Chen, Ruiqi, et al.
Published: (2024)
Hardware for converting floating-point to the microscaling (MX) format
by: Gorodecky, Danila, et al.
Published: (2024)
by: Gorodecky, Danila, et al.
Published: (2024)
An Efficient Sparse Hardware Accelerator for Spike-Driven Transformer
by: Li, Zhengke, et al.
Published: (2025)
by: Li, Zhengke, et al.
Published: (2025)
Synapse: Virtualizing Match Tables in Programmable Hardware
by: Lahmer, Seyyidahmed, et al.
Published: (2025)
by: Lahmer, Seyyidahmed, et al.
Published: (2025)
Residue Number System (RNS) based Distributed Quantum Multiplication
by: Gaur, Bhaskar, et al.
Published: (2025)
by: Gaur, Bhaskar, et al.
Published: (2025)
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
by: Agarwal, Ayushi, et al.
Published: (2026)
by: Agarwal, Ayushi, et al.
Published: (2026)
Karatsuba Matrix Multiplication and its Efficient Custom Hardware Implementations
by: Pogue, Trevor E., et al.
Published: (2025)
by: Pogue, Trevor E., et al.
Published: (2025)
Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads
by: Popovici, Doru Thom, et al.
Published: (2025)
by: Popovici, Doru Thom, et al.
Published: (2025)
Energy-Efficient Hardware Acceleration of Whisper ASR on a CGLA
by: Ando, Takuto, et al.
Published: (2025)
by: Ando, Takuto, et al.
Published: (2025)
Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects
by: Ramsauer, Ralf, et al.
Published: (2022)
by: Ramsauer, Ralf, et al.
Published: (2022)
Taming Performance Variability caused by Client-Side Hardware Configuration
by: Antoniou, Georgia, et al.
Published: (2024)
by: Antoniou, Georgia, et al.
Published: (2024)
Hardware Acceleration in Portable MRIs: State of the Art and Future Prospects
by: Habsi, Omar Al, et al.
Published: (2025)
by: Habsi, Omar Al, et al.
Published: (2025)
Xpikeformer: Hybrid Analog-Digital Hardware Acceleration for Spiking Transformers
by: Song, Zihang, et al.
Published: (2024)
by: Song, Zihang, et al.
Published: (2024)
CHAOS: Controlled Hardware fAult injectOr System for gem5
by: Vinciguerra, Elio, et al.
Published: (2026)
by: Vinciguerra, Elio, et al.
Published: (2026)
TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
by: Tozlu, Yavuz Selim, et al.
Published: (2026)
by: Tozlu, Yavuz Selim, et al.
Published: (2026)
HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV
by: Shijie, Liu, et al.
Published: (2026)
by: Shijie, Liu, et al.
Published: (2026)
From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
by: Fu, Weimin, et al.
Published: (2026)
by: Fu, Weimin, et al.
Published: (2026)
Linear Complexity Fermionic Simulation on Quantum Devices with Hardware Connectivity Constraints
by: Gao, Xiangyu, et al.
Published: (2026)
by: Gao, Xiangyu, et al.
Published: (2026)
GenDRAM:Hardware-Software Co-Design of General Platform in DRAM
by: Lu, Tsung-Han, et al.
Published: (2026)
by: Lu, Tsung-Han, et al.
Published: (2026)
FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training
by: Lu, Jinming, et al.
Published: (2025)
by: Lu, Jinming, et al.
Published: (2025)
Similar Items
-
Mirage: An RNS-Based Photonic Accelerator for DNN Training
by: Demirkiran, Cansu, et al.
Published: (2023) -
Memory-Guided Unified Hardware Accelerator for Mixed-Precision Scientific Computing
by: Wang, Chuanzhen, et al.
Published: (2026) -
Rescaling-Aware Training for Efficient Deployment of Deep Learning Models on Full-Integer Hardware
by: Mueller, Lion, et al.
Published: (2025) -
SoftmAP: Software-Hardware Co-design for Integer-Only Softmax on Associative Processors
by: Rakka, Mariam, et al.
Published: (2024) -
Digit-Recurrence Posit Division
by: Murillo, Raul, et al.
Published: (2025)