Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit -- A P-Bit
Fuente:
arXiv
Enregistré dans:
| Auteurs principaux: | , , , , |
|---|---|
| Format: | Preprint |
| Publié: |
2026
|
| Sujets: | |
| Accès en ligne: | |
| Tags: |
Ajouter un tag
Pas de tags, Soyez le premier à ajouter un tag!
|
| _version_ | 1866911624860794880 |
|---|---|
| author | Zhang, Xuejian Daniel, John Arnesh Divakaruni Dilley, Neil Chen, Zhihong Appenzeller, Joerg |
| author_facet | Zhang, Xuejian Daniel, John Arnesh Divakaruni Dilley, Neil Chen, Zhihong Appenzeller, Joerg |
| contents | Ongoing semiconductor scaling challenges and the rise of neuromorphic computing have sparked interest in exploring novel computing schemes to achieve higher power efficiency and computational capabilities. Probabilistic computing is one candidate that endows low power consumption, capability of solving probability-encoded computational problems, and the ease of integration with existing CMOS technology. A basic building block of this scheme is the probabilistic bit (P-Bit), which utilizes a novel device such as a stochastic magnetic tunnel junction (sMTJ) to generate tunable randomness by nature. This work presents the first experimental demonstration of a fully CMOS-integrated sMTJ-based P-Bit, capable of generating rail-to-rail stochastic output with a mere collection of 3 transistors + 1 sMTJ. Furthermore, simulations also confirm this P-Bit's functionality in probabilistic logic circuits. The demonstration of such P-Bit paves the way towards realizing monolithic large-scale probabilistic computing architecture on CMOS chips. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_05191 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit -- A P-Bit Zhang, Xuejian Daniel, John Arnesh Divakaruni Dilley, Neil Chen, Zhihong Appenzeller, Joerg Emerging Technologies Ongoing semiconductor scaling challenges and the rise of neuromorphic computing have sparked interest in exploring novel computing schemes to achieve higher power efficiency and computational capabilities. Probabilistic computing is one candidate that endows low power consumption, capability of solving probability-encoded computational problems, and the ease of integration with existing CMOS technology. A basic building block of this scheme is the probabilistic bit (P-Bit), which utilizes a novel device such as a stochastic magnetic tunnel junction (sMTJ) to generate tunable randomness by nature. This work presents the first experimental demonstration of a fully CMOS-integrated sMTJ-based P-Bit, capable of generating rail-to-rail stochastic output with a mere collection of 3 transistors + 1 sMTJ. Furthermore, simulations also confirm this P-Bit's functionality in probabilistic logic circuits. The demonstration of such P-Bit paves the way towards realizing monolithic large-scale probabilistic computing architecture on CMOS chips. |
| title | Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit -- A P-Bit |
| topic | Emerging Technologies |
| url | https://arxiv.org/abs/2604.05191 |