Imagen de Portada

Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit -- A P-Bit

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Zhang, Xuejian, Daniel, John Arnesh Divakaruni, Dilley, Neil, Chen, Zhihong, Appenzeller, Joerg
Formato:	Preprint
Publicado:	2026
Materias:	Emerging Technologies
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS2 FETs
por: Daniel, John, et al.
Publicado: (2023)

From Bits to Qubits: Challenges in Classical-Quantum Integration
por: Kulkarni, Sudhanshu Pravin, et al.
Publicado: (2025)

pc-COP: An Efficient and Configurable 2048-p-Bit Fully-Connected Probabilistic Computing Accelerator for Combinatorial Optimization
por: Magar, Kiran, et al.
Publicado: (2025)

3SAT on an All-to-All-Connected CMOS Ising Solver Chip
por: Cılasun, Hüsrev, et al.
Publicado: (2023)

Efficient FIR filtering with Bit Layer Multiply Accumulator
por: Liguori, Vincenzo
Publicado: (2024)

Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM
por: Hajisadeghi, Amir M., et al.
Publicado: (2024)

FAMES: Fast Approximate Multiplier Substitution for Mixed-Precision Quantized DNNs--Down to 2 Bits!
por: Ren, Yi, et al.
Publicado: (2024)

A Comparison of 163‐Bit Hybrid Karatsuba Multiplier and Word‐Serial Multipliers for ECC Processors
por: Sumit Singh Dhanda, et al.
Publicado: (2025)

BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks
por: Bührer, Simon, et al.
Publicado: (2026)

WAGONN: Weight Bit Agglomeration in Crossbar Arrays for Reduced Impact of Interconnect Resistance on DNN Inference Accuracy
por: Victor, Jeffry, et al.
Publicado: (2024)

CMOS 2.0 -- Redefining the Future of Scaling
por: Brunion, Moritz, et al.
Publicado: (2025)

Hybrid CMOS/Memristor Circuit Design Methodology
por: Maheshwari, Sachin, et al.
Publicado: (2020)

PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro with In-Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout
por: Chen, Zhiyu, et al.
Publicado: (2024)

A 5T-2MTJ STT-assisted Spin Orbit Torque based Ternary Content Addressable Memory for Hardware Accelerators
por: Narla, Siri, et al.
Publicado: (2024)

Versatile CMOS Analog LIF Neuron for Memristor-Integrated Neuromorphic Circuits
por: Garg, Nikhil, et al.
Publicado: (2024)

CMOS-integrated superparamagnetic tunnel junction-based p-bit
por: Yoon, Ju-Young, et al.
Publicado: (2026)

Temperature-Resilient Analog Neuromorphic Chip in Single-Polysilicon CMOS Technology
por: Rizzo, Tommaso, et al.
Publicado: (2024)

Cost-Effective Realization of n-Bit Toffoli Gates for IBM Quantum Computers Using the Bloch Sphere Approach and IBM Native Gates
por: Al-Bayaty, Ali, et al.
Publicado: (2024)

Bit-Vector Abstractions to Formally Verify Quantum Error Detection & Entanglement
por: Govindankutty, Arun
Publicado: (2026)

Fused-MemBrain: a spiking processor combining CMOS and self-assembled memristive networks
por: Cipollini, Davide, et al.
Publicado: (2024)

A 3D Memristor Architecture for In-Memory Computing Demonstrated with SHA3
por: Aljafar, Muayad J., et al.
Publicado: (2024)

Efficient Reprogramming of Memristive Crossbars for DNNs: Weight Sorting and Bit Stucking
por: Farias, Matheus, et al.
Publicado: (2024)

Green Probabilistic Semantic Communication over Wireless Networks
por: Xu, Ruopeng, et al.
Publicado: (2024)

NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors
por: Nair, Harideep, et al.
Publicado: (2024)

Extractive summarization on a CMOS Ising machine
por: Zeng, Ziqing, et al.
Publicado: (2026)

Implementation of transformer-based LLMs with large-scale optoelectronic neurons on a CMOS compatible platform
por: Na, Neil, et al.
Publicado: (2025)

Hardware-Algorithm Co-Design for Hyperdimensional Computing Based on Memristive System-on-Chip
por: Huang, Yi, et al.
Publicado: (2025)

First Demonstration of 28 nm Fabricated FeFET-Based Nonvolatile 6T SRAM
por: Mema, Albi, et al.
Publicado: (2026)

Energy Efficient Knapsack Optimization Using Probabilistic Memristor Crossbars
por: Li, Jinzhan, et al.
Publicado: (2024)

Concept of a System-on-Chip Research Platform Benchmarking Interaction of Memristor-based Bio-inspired Computing Paradigms
por: Grewing, Christian, et al.
Publicado: (2025)

SuperSNN: A Hardware-Aware Framework for Physically Realizable, High-Performance Superconducting Spiking Neural Network Chips
por: Song, Changxu, et al.
Publicado: (2025)

Integration of Physics-Derived Memristor Models with Machine Learning Frameworks
por: Yu, Zhenming, et al.
Publicado: (2024)

AI-Guided Codesign Framework for Novel Material and Device Design applied to MTJ-based True Random Number Generators
por: Patel, Karan P., et al.
Publicado: (2024)

Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine
por: Gonul, Yilmaz Ege, et al.
Publicado: (2025)

Spectral Convolutional Neural Network Chip for In-sensor Edge Computing of Incoherent Natural Light
por: Cui, Kaiyu, et al.
Publicado: (2023)

Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning
por: Manna, Bibhas, et al.
Publicado: (2023)

16-channel Photonic Solver for Optimization Problems on a Silicon Chip
por: Ouyang, Jiayi, et al.
Publicado: (2024)

Demonstration of 3 V Programmable Josephson Junction Arrays Using Non-Integer-Multiple Logic
por: Cao, Wenhui, et al.
Publicado: (2024)

EDA-Q: Electronic Design Automation for Superconducting Quantum Chip
por: Zhao, Bo, et al.
Publicado: (2025)

High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians
por: Onizawa, Naoya, et al.
Publicado: (2026)