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| Hauptverfasser: | , , |
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| Format: | Preprint |
| Veröffentlicht: |
2026
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| Online-Zugang: | https://arxiv.org/abs/2604.05313 |
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| _version_ | 1866911571434799104 |
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| author | Wang, Yihui Peng, Sheng-Yu Shah, Sahil |
| author_facet | Wang, Yihui Peng, Sheng-Yu Shah, Sahil |
| contents | This paper presents a fully synthesizable, treebased Address-Event Representation (AER) encoder designed for scalable neuromorphic computing systems. To achieve high throughput while maintaining strict compatibility with commercial EDA workflows, the asynchronous design employs a bundled-data protocol within a semi-decoupled micropipeline. The architecture replaces traditional transparent latches with standard edge-triggered flip-flops, enabling digital synthesis and place-and-route (PnR) using Cadence toolkits. A cross-coupled NAND-based random-priority arbiter is embedded within the encoder of each tree node to resolve event collisions efficiently. An 8-event AER prototype is fabricated in 65 nm CMOS technology utilizing a purely digital standard-cell flow. Post-fabrication silicon measurements validate the design, demonstrating a peak throughput of 33 MEvent/s and an average event latency of 50 ns, equating to a propagation delay of 17 ns/(event-bit). The design consumes only 435 fJ per encoded event. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_05313 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | An Ultra-Low-Power Synthesizable Asynchronous AER Encoder for Neuromorphic Edge Devices Wang, Yihui Peng, Sheng-Yu Shah, Sahil Systems and Control This paper presents a fully synthesizable, treebased Address-Event Representation (AER) encoder designed for scalable neuromorphic computing systems. To achieve high throughput while maintaining strict compatibility with commercial EDA workflows, the asynchronous design employs a bundled-data protocol within a semi-decoupled micropipeline. The architecture replaces traditional transparent latches with standard edge-triggered flip-flops, enabling digital synthesis and place-and-route (PnR) using Cadence toolkits. A cross-coupled NAND-based random-priority arbiter is embedded within the encoder of each tree node to resolve event collisions efficiently. An 8-event AER prototype is fabricated in 65 nm CMOS technology utilizing a purely digital standard-cell flow. Post-fabrication silicon measurements validate the design, demonstrating a peak throughput of 33 MEvent/s and an average event latency of 50 ns, equating to a propagation delay of 17 ns/(event-bit). The design consumes only 435 fJ per encoded event. |
| title | An Ultra-Low-Power Synthesizable Asynchronous AER Encoder for Neuromorphic Edge Devices |
| topic | Systems and Control |
| url | https://arxiv.org/abs/2604.05313 |