FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration
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arXiv
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| Autores principales: | , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866908953644892160 |
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| author | Chen, Xingzhen Zhuang, Jinming Yang, Zhuoping Ji, Shixin Schultz, Sarah Dong, Zheng Shi, Weisong Zhou, Peipei |
| author_facet | Chen, Xingzhen Zhuang, Jinming Yang, Zhuoping Ji, Shixin Schultz, Sarah Dong, Zheng Shi, Weisong Zhou, Peipei |
| contents | With the development of deep neural network (DNN) enabled applications, achieving high hardware resource efficiency on diverse workloads is non-trivial in heterogeneous computing platforms. Prior works discuss dedicated architectures to achieve maximal resource efficiency. However, a mismatch between hardware and workloads always exists in various diverse workloads. Other works discuss overlay architecture that can dynamically switch dataflow for different workloads. However, these works are still limited by flexibility granularity and induce much resource inefficiency. To solve this problem, we propose a flexible composing architecture, FILCO, that can efficiently match diverse workloads to achieve the optimal storage and computation resource efficiency. FILCO can be reconfigured in real-time and flexibly composed into a unified or multiple independent accelerators. We also propose the FILCO framework, including an analytical model with a two-stage DSE that can achieve the optimal design point. We also evaluate the FILCO framework on the 7nm AMD Versal VCK190 board. Compared with prior works, our design can achieve 1.3x - 5x throughput and hardware efficiency on various diverse workloads. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_07523 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration Chen, Xingzhen Zhuang, Jinming Yang, Zhuoping Ji, Shixin Schultz, Sarah Dong, Zheng Shi, Weisong Zhou, Peipei Hardware Architecture With the development of deep neural network (DNN) enabled applications, achieving high hardware resource efficiency on diverse workloads is non-trivial in heterogeneous computing platforms. Prior works discuss dedicated architectures to achieve maximal resource efficiency. However, a mismatch between hardware and workloads always exists in various diverse workloads. Other works discuss overlay architecture that can dynamically switch dataflow for different workloads. However, these works are still limited by flexibility granularity and induce much resource inefficiency. To solve this problem, we propose a flexible composing architecture, FILCO, that can efficiently match diverse workloads to achieve the optimal storage and computation resource efficiency. FILCO can be reconfigured in real-time and flexibly composed into a unified or multiple independent accelerators. We also propose the FILCO framework, including an analytical model with a two-stage DSE that can achieve the optimal design point. We also evaluate the FILCO framework on the 7nm AMD Versal VCK190 board. Compared with prior works, our design can achieve 1.3x - 5x throughput and hardware efficiency on various diverse workloads. |
| title | FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.07523 |