From LLM to Silicon: RL-Driven ASIC Architecture Exploration for On-Device AI Inference
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arXiv
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| Autores principales: | , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866918435741499392 |
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| author | Ganti, Ravindra Xu, Steve |
| author_facet | Ganti, Ravindra Xu, Steve |
| contents | We present an RL-driven compiler that jointly optimizes ASIC architecture, memory hierarchy, and workload partitioning for AI inference across 3nm to 28nm. The design space is formulated as a single Markov Decision Process with mixed discrete-continuous actions and a unified Power-Performance-Area (PPA) objective. Soft Actor-Critic (SAC) with Mixture-of-Experts gating explores the joint space of mesh topology, per-core microarchitecture, and operator placement. We validate on two workloads, Llama 3.1 8B FP16 (high-performance mode, 29809 tokens per second at 3nm) and SmolVLM (low-power mode, less than 13 mW at all nodes, 10 MHz). Across 7 process nodes, the RL automatically adapts mesh sizes and per-tile configurations, including heterogeneous FETCH, VLEN, and memory allocation without node-specific manual retuning. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_07526 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | From LLM to Silicon: RL-Driven ASIC Architecture Exploration for On-Device AI Inference Ganti, Ravindra Xu, Steve Hardware Architecture Machine Learning We present an RL-driven compiler that jointly optimizes ASIC architecture, memory hierarchy, and workload partitioning for AI inference across 3nm to 28nm. The design space is formulated as a single Markov Decision Process with mixed discrete-continuous actions and a unified Power-Performance-Area (PPA) objective. Soft Actor-Critic (SAC) with Mixture-of-Experts gating explores the joint space of mesh topology, per-core microarchitecture, and operator placement. We validate on two workloads, Llama 3.1 8B FP16 (high-performance mode, 29809 tokens per second at 3nm) and SmolVLM (low-power mode, less than 13 mW at all nodes, 10 MHz). Across 7 process nodes, the RL automatically adapts mesh sizes and per-tile configurations, including heterogeneous FETCH, VLEN, and memory allocation without node-specific manual retuning. |
| title | From LLM to Silicon: RL-Driven ASIC Architecture Exploration for On-Device AI Inference |
| topic | Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2604.07526 |