Trilinear Compute-in-Memory Architecture for Energy-Efficient Transformer Acceleration
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arXiv
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| Autores principales: | , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866915926248521728 |
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| author | Mia, Md Zesun Ahmed Duan, Jiahui Ni, Kai Sengupta, Abhronil |
| author_facet | Mia, Md Zesun Ahmed Duan, Jiahui Ni, Kai Sengupta, Abhronil |
| contents | Self-attention in Transformers generates dynamic operands that force conventional Compute-in-Memory (CIM) accelerators into costly non-volatile memory (NVM) reprogramming cycles, degrading throughput and stressing device endurance. Existing solutions either reduce but retain NVM writes through matrix decomposition or sparsity, or move attention computation to digital CMOS at the expense of NVM density. We present TrilinearCIM, a Double-Gate FeFET (DG-FeFET)-based architecture that uses back-gate modulation to realize a three-operand multiply-accumulate primitive for in-memory attention computation without dynamic ferroelectric reprogramming. Evaluated on BERT-base (GLUE) and ViT-base (ImageNet and CIFAR), TrilinearCIM outperforms conventional CIM on seven of nine GLUE tasks while achieving up to 46.6\% energy reduction and 20.4\% latency improvement over conventional FeFET CIM at 37.3\% area overhead. To our knowledge, this is the first architecture to perform complete Transformer attention computation exclusively in NVM cores without runtime reprogramming. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_07628 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Trilinear Compute-in-Memory Architecture for Energy-Efficient Transformer Acceleration Mia, Md Zesun Ahmed Duan, Jiahui Ni, Kai Sengupta, Abhronil Hardware Architecture Emerging Technologies Neural and Evolutionary Computing Self-attention in Transformers generates dynamic operands that force conventional Compute-in-Memory (CIM) accelerators into costly non-volatile memory (NVM) reprogramming cycles, degrading throughput and stressing device endurance. Existing solutions either reduce but retain NVM writes through matrix decomposition or sparsity, or move attention computation to digital CMOS at the expense of NVM density. We present TrilinearCIM, a Double-Gate FeFET (DG-FeFET)-based architecture that uses back-gate modulation to realize a three-operand multiply-accumulate primitive for in-memory attention computation without dynamic ferroelectric reprogramming. Evaluated on BERT-base (GLUE) and ViT-base (ImageNet and CIFAR), TrilinearCIM outperforms conventional CIM on seven of nine GLUE tasks while achieving up to 46.6\% energy reduction and 20.4\% latency improvement over conventional FeFET CIM at 37.3\% area overhead. To our knowledge, this is the first architecture to perform complete Transformer attention computation exclusively in NVM cores without runtime reprogramming. |
| title | Trilinear Compute-in-Memory Architecture for Energy-Efficient Transformer Acceleration |
| topic | Hardware Architecture Emerging Technologies Neural and Evolutionary Computing |
| url | https://arxiv.org/abs/2604.07628 |