A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators
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arXiv
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| Main Authors: | , , , , , , , , , , , , , |
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| Format: | Preprint |
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2026
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| _version_ | 1866910115968319488 |
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| author | Li, Cong Xue, Chenhao Ren, Yi Dong, Xiping Cheng, Yu Hu, Yinbo Bai, Fujun Guo, Yixin Jiang, Xiping Wu, Qiang Yang, Zhi Cheng, Zhe Xie, Yuan Sun, Guangyu |
| author_facet | Li, Cong Xue, Chenhao Ren, Yi Dong, Xiping Cheng, Yu Hu, Yinbo Bai, Fujun Guo, Yixin Jiang, Xiping Wu, Qiang Yang, Zhi Cheng, Zhe Xie, Yuan Sun, Guangyu |
| contents | Large language models (LLMs) exhibit memory-intensive behavior during decoding, making it a key bottleneck in LLM inference. To accelerate decoding execution, hybrid-bonding-based 3D-DRAM has been adopted in LLM accelerators. While this emerging technology provides strong performance gains over existing hardware, current 3D-DRAM accelerators (3D-Accelerators) rely on closed-source evaluation tools, limiting access to publicly available performance analysis methods. Moreover, existing designs are highly customized for specific scenarios, lacking a general and reusable full-stack modeling for 3D-Accelerators across diverse usecases.
To bridge this fundamental gap, we present ATLAS, the first silicon-proven Architectural Three-dimesional-DRAM-based LLM Accelerator Simulation framework. Built on commercially deployed multi-layer 3D-DRAM technology, ATLAS introduces unified abstractions for both 3D-Accelerator system architecture and programming primitives to support arbitrary LLM inference scenarios. Validation against real silicon shows that ATLAS achieves $\le$8.57% simulation error and 97.26-99.96\% correlation with measured performance. Through design space exploration with ATLAS, we demonstrate its ability to guide architecture design and distill key takeaways for both 3D-DRAM memory system and 3D-Accelerator microarchitecture across scenarios. ATLAS will be open-sourced upon publication, enabling further research on 3D-Accelerators. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2604_08044 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators Li, Cong Xue, Chenhao Ren, Yi Dong, Xiping Cheng, Yu Hu, Yinbo Bai, Fujun Guo, Yixin Jiang, Xiping Wu, Qiang Yang, Zhi Cheng, Zhe Xie, Yuan Sun, Guangyu Hardware Architecture Large language models (LLMs) exhibit memory-intensive behavior during decoding, making it a key bottleneck in LLM inference. To accelerate decoding execution, hybrid-bonding-based 3D-DRAM has been adopted in LLM accelerators. While this emerging technology provides strong performance gains over existing hardware, current 3D-DRAM accelerators (3D-Accelerators) rely on closed-source evaluation tools, limiting access to publicly available performance analysis methods. Moreover, existing designs are highly customized for specific scenarios, lacking a general and reusable full-stack modeling for 3D-Accelerators across diverse usecases. To bridge this fundamental gap, we present ATLAS, the first silicon-proven Architectural Three-dimesional-DRAM-based LLM Accelerator Simulation framework. Built on commercially deployed multi-layer 3D-DRAM technology, ATLAS introduces unified abstractions for both 3D-Accelerator system architecture and programming primitives to support arbitrary LLM inference scenarios. Validation against real silicon shows that ATLAS achieves $\le$8.57% simulation error and 97.26-99.96\% correlation with measured performance. Through design space exploration with ATLAS, we demonstrate its ability to guide architecture design and distill key takeaways for both 3D-DRAM memory system and 3D-Accelerator microarchitecture across scenarios. ATLAS will be open-sourced upon publication, enabling further research on 3D-Accelerators. |
| title | A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.08044 |