From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation
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arXiv
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| Autori principali: | , , , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866913021040787456 |
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| author | Wang, Yonghao Lyu, Hongqin Chen, Boling Bao, MinYang Ding, Wenchao Gu, Feng Chao, Zhiteng Mu, Jianan Shi, Kan Wang, Tiancheng Li, Huawei |
| author_facet | Wang, Yonghao Lyu, Hongqin Chen, Boling Bao, MinYang Ding, Wenchao Gu, Feng Chao, Zhiteng Mu, Jianan Shi, Kan Wang, Tiancheng Li, Huawei |
| contents | Functional verification has become the most time-consuming phase in IC development, and Assertion-Based Verification (ABV) is key to reducing debugging time. However, existing LLM-based assertion generation methods typically pursue indiscriminate verification, aiming for maximal coverage without considering signal criticality, whereas industrial practice demands maximizing coverage with minimal verification cost. Consequently, identifying signals that have the greatest impact on design functionality and error propagation-enabling a shift from indiscriminate to targeted verification-remains a key challenge. To address this, we propose AgileAssert, a key signal-driven assertion generation framework that constructs RTL semantic graphs and identifies the top-K critical signals via a hybrid scoring and selection mechanism, followed by structure-aware RTL slicing to provide the LLM with precise targets and contextual information, thereby guiding LLMs to generate tightly constrained targeted assertions for efficient verification. Evaluated on block- and CPU-level designs, with an average 66.68% reduction in assertions, our approach outperforms three existing SOTA methods, and significantly improving coverage metrics while reducing input token consumption by 64%. In mutation testing, when our approach surpasses existing methods in error detection rate, the average number of assertions used decreases by 72.74%. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_08932 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation Wang, Yonghao Lyu, Hongqin Chen, Boling Bao, MinYang Ding, Wenchao Gu, Feng Chao, Zhiteng Mu, Jianan Shi, Kan Wang, Tiancheng Li, Huawei Hardware Architecture Functional verification has become the most time-consuming phase in IC development, and Assertion-Based Verification (ABV) is key to reducing debugging time. However, existing LLM-based assertion generation methods typically pursue indiscriminate verification, aiming for maximal coverage without considering signal criticality, whereas industrial practice demands maximizing coverage with minimal verification cost. Consequently, identifying signals that have the greatest impact on design functionality and error propagation-enabling a shift from indiscriminate to targeted verification-remains a key challenge. To address this, we propose AgileAssert, a key signal-driven assertion generation framework that constructs RTL semantic graphs and identifies the top-K critical signals via a hybrid scoring and selection mechanism, followed by structure-aware RTL slicing to provide the LLM with precise targets and contextual information, thereby guiding LLMs to generate tightly constrained targeted assertions for efficient verification. Evaluated on block- and CPU-level designs, with an average 66.68% reduction in assertions, our approach outperforms three existing SOTA methods, and significantly improving coverage metrics while reducing input token consumption by 64%. In mutation testing, when our approach surpasses existing methods in error detection rate, the average number of assertions used decreases by 72.74%. |
| title | From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.08932 |