Aging Aware Adaptive Voltage Scaling for Reliable and Efficient AI Accelerators
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arXiv
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| Auteurs principaux: | , , , , , |
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| Format: | Preprint |
| Publié: |
2026
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| _version_ | 1866908954494238720 |
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| author | Xie, Tong Zhang, Zuodong Yang, Chao Wang, Yuan Wang, Runsheng Li, Meng |
| author_facet | Xie, Tong Zhang, Zuodong Yang, Chao Wang, Yuan Wang, Runsheng Li, Meng |
| contents | Deep neural networks (DNNs) have showcased remarkable performance across various tasks and are widely deployed on AI accelerators fabricated in advanced technology nodes for efficiency. As aging effects become more pronounced, timing and voltage guardbands are increasingly applied. Aging-aware adaptive voltage scaling (AVS), which adjusts supply voltage based on on-chip aging scenarios, has emerged as a promising solution to avoid excessive guardbanding. However, conventional AVS techniques overlook the inherent resilience of DNNs and frequently raise the supply voltage unnecessarily, thereby exacerbating aging and increasing power consumption. To enable reliable and efficient AI inference with AVS, in this paper, we develop an accurate aging prediction framework that incorporates historical effects and iterative extrapolation for full-lifetime modeling. Building on this framework, we propose a fault-tolerant voltage scaling policy that exploits DNN resilience and defers voltage increases accordingly. Experiments show that our framework mitigates the pessimism of maximum-voltage baselines, reducing predicted threshold voltage shift (ΔVth) by 19.4% for PMOS and 19.1% for NMOS, respectively. Furthermore, evaluation on representative DNN workloads demonstrates that our optimization reduces aging degradation by up to 45.8% (NMOS) and 30.6% (PMOS) while achieving 14.0% average lifetime power savings compared to resilience-agnostic methods. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_09994 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Aging Aware Adaptive Voltage Scaling for Reliable and Efficient AI Accelerators Xie, Tong Zhang, Zuodong Yang, Chao Wang, Yuan Wang, Runsheng Li, Meng Hardware Architecture Deep neural networks (DNNs) have showcased remarkable performance across various tasks and are widely deployed on AI accelerators fabricated in advanced technology nodes for efficiency. As aging effects become more pronounced, timing and voltage guardbands are increasingly applied. Aging-aware adaptive voltage scaling (AVS), which adjusts supply voltage based on on-chip aging scenarios, has emerged as a promising solution to avoid excessive guardbanding. However, conventional AVS techniques overlook the inherent resilience of DNNs and frequently raise the supply voltage unnecessarily, thereby exacerbating aging and increasing power consumption. To enable reliable and efficient AI inference with AVS, in this paper, we develop an accurate aging prediction framework that incorporates historical effects and iterative extrapolation for full-lifetime modeling. Building on this framework, we propose a fault-tolerant voltage scaling policy that exploits DNN resilience and defers voltage increases accordingly. Experiments show that our framework mitigates the pessimism of maximum-voltage baselines, reducing predicted threshold voltage shift (ΔVth) by 19.4% for PMOS and 19.1% for NMOS, respectively. Furthermore, evaluation on representative DNN workloads demonstrates that our optimization reduces aging degradation by up to 45.8% (NMOS) and 30.6% (PMOS) while achieving 14.0% average lifetime power savings compared to resilience-agnostic methods. |
| title | Aging Aware Adaptive Voltage Scaling for Reliable and Efficient AI Accelerators |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.09994 |