Late Breaking Results: CHESSY: Coupled Hybrid Emulation with SystemC-FPGA Synchronization
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arXiv
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| Auteurs principaux: | , , , , , , , , , |
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| Format: | Preprint |
| Publié: |
2026
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| _version_ | 1866910121194422272 |
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| author | Ruotolo, Lorenzo Pollo, Giovanni Hamdi, Mohamed Amine Risso, Matteo Chen, Yukai Macii, Enrico Poncino, Massimo Vinco, Sara Burrello, Alessio Pagliari, Daniele Jahier |
| author_facet | Ruotolo, Lorenzo Pollo, Giovanni Hamdi, Mohamed Amine Risso, Matteo Chen, Yukai Macii, Enrico Poncino, Massimo Vinco, Sara Burrello, Alessio Pagliari, Daniele Jahier |
| contents | The growing complexity of cyber-physical systems (CPSs) calls for early prototyping tools that combine accuracy, speed, and usability. Virtual Platforms (VPs) provide fast functional simulation, but hybrid co-emulation solutions, in which key digital components are deployed on FPGA, become necessary when accurate timing modelling is required and RTL simulation is too costly. However, existing hybrid emulation tools are mostly proprietary, and rely on vendor-specific FPGA features. To address this gap, we introduce an open-source framework that connects SystemC-based VPs with FPGA emulation, enabling full-system co-emulation of digital and non-digital components. The FPGA accelerates the execution of main digital subsystems, while a wrapper coordinates timing and communication with the VP through JTAG, maintaining synchronization with simulated peripherals. Evaluations using a RISC-V SoC, with an example in the biosignals processing domain, show up to 2500x speedup compared to RTL simulation, while maintaining less than 2x total simulation time relative to pure FPGA emulation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_10093 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Late Breaking Results: CHESSY: Coupled Hybrid Emulation with SystemC-FPGA Synchronization Ruotolo, Lorenzo Pollo, Giovanni Hamdi, Mohamed Amine Risso, Matteo Chen, Yukai Macii, Enrico Poncino, Massimo Vinco, Sara Burrello, Alessio Pagliari, Daniele Jahier Hardware Architecture The growing complexity of cyber-physical systems (CPSs) calls for early prototyping tools that combine accuracy, speed, and usability. Virtual Platforms (VPs) provide fast functional simulation, but hybrid co-emulation solutions, in which key digital components are deployed on FPGA, become necessary when accurate timing modelling is required and RTL simulation is too costly. However, existing hybrid emulation tools are mostly proprietary, and rely on vendor-specific FPGA features. To address this gap, we introduce an open-source framework that connects SystemC-based VPs with FPGA emulation, enabling full-system co-emulation of digital and non-digital components. The FPGA accelerates the execution of main digital subsystems, while a wrapper coordinates timing and communication with the VP through JTAG, maintaining synchronization with simulated peripherals. Evaluations using a RISC-V SoC, with an example in the biosignals processing domain, show up to 2500x speedup compared to RTL simulation, while maintaining less than 2x total simulation time relative to pure FPGA emulation. |
| title | Late Breaking Results: CHESSY: Coupled Hybrid Emulation with SystemC-FPGA Synchronization |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.10093 |