From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866914466567815168 |
|---|---|
| author | Zhang, Jie Guan, Jiapeng Zhou, Hao Han, Xiaomeng Wang, Tinglue Wei, Ran Jiang, Zhe |
| author_facet | Zhang, Jie Guan, Jiapeng Zhou, Hao Han, Xiaomeng Wang, Tinglue Wei, Ran Jiang, Zhe |
| contents | Block Floating-Point (BFP) is emerging as an attractive data format for edge Neural Processing Units (NPUs), combining wide dynamic range with high hardware efficiency. However, its behavior under hardware faults and suitability for safety-critical deployments remain underexplored. Here, we present the first in-depth empirical reliability study of BFP-based NPUs. Using RTL-level fault injection on NPUs, our bit- and path-level analysis reveals pronounced heterogeneous vulnerabilities and shows conventional end-to-end check becomes ineffective under nonlinear block scaling. Guided by these insights, we design a fault-tolerant BFP-based NPU microarchitecture that aligns the BFP computational semantics with reliability constraints. The design uses a row/column-wise blocking strategy to decouple the fixed-point mantissa computations from the scalar exponent path, and introduces ultra-lightweight protection mechanisms for each. Experimental results demonstrate our design achieves near-dual modular redundancy reliability with only $3.55\%$ geometric mean performance overhead and less than $2\%$ hardware cost. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_10494 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU Zhang, Jie Guan, Jiapeng Zhou, Hao Han, Xiaomeng Wang, Tinglue Wei, Ran Jiang, Zhe Hardware Architecture Block Floating-Point (BFP) is emerging as an attractive data format for edge Neural Processing Units (NPUs), combining wide dynamic range with high hardware efficiency. However, its behavior under hardware faults and suitability for safety-critical deployments remain underexplored. Here, we present the first in-depth empirical reliability study of BFP-based NPUs. Using RTL-level fault injection on NPUs, our bit- and path-level analysis reveals pronounced heterogeneous vulnerabilities and shows conventional end-to-end check becomes ineffective under nonlinear block scaling. Guided by these insights, we design a fault-tolerant BFP-based NPU microarchitecture that aligns the BFP computational semantics with reliability constraints. The design uses a row/column-wise blocking strategy to decouple the fixed-point mantissa computations from the scalar exponent path, and introduces ultra-lightweight protection mechanisms for each. Experimental results demonstrate our design achieves near-dual modular redundancy reliability with only $3.55\%$ geometric mean performance overhead and less than $2\%$ hardware cost. |
| title | From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.10494 |