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Main Authors: Choi, Ilhuan, Yoo, Jiwon, Lee, Yoona, Jeong, Yewon, Lee, Jason Jaesung, Choi, Woo-Seok
Format: Preprint
Published: 2026
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Online Access:https://arxiv.org/abs/2604.12420
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author Choi, Ilhuan
Yoo, Jiwon
Lee, Yoona
Jeong, Yewon
Lee, Jason Jaesung
Choi, Woo-Seok
author_facet Choi, Ilhuan
Yoo, Jiwon
Lee, Yoona
Jeong, Yewon
Lee, Jason Jaesung
Choi, Woo-Seok
contents Write-and-verify (WV) is essential for programming multi-level RRAM weights, yet under scaled-voltage and low-SNR conditions the verify read increasingly limits mapping accuracy, convergence speed and energy. We propose a Hadamard-domain WV framework that improves verify reliability without adding analog hardware. % without introducing additional analog blocks % while leveraging the existing analog front-end \emph{HD-PV} (Hadamard-Encoded Parallel-Verify) replaces conventional one-hot verify reads with $N$ orthogonal Hadamard patterns for an $N$-cell column. Changing the read basis without increasing the column-level read count, inverse Hadamard decoding reduces uncorrelated read-noise variance by a factor of $N$ and cancels common-mode disturbances. \emph{HARP} (Hadamard-based ADC-Energy-Reduced Parallel-Verify) further exploits the fact that WV needs only ternary update decisions, not full digital codes, and replaces SAR conversions with lightweight compare-only operations. Across CIFAR-10, CIFAR-100, and keyword spotting under severe read noise, conventional WV loses over 20\,\% accuracy on CIFAR-10, while HD-PV and HARP limit the loss to 0.6\,\% and 1\,\% under the same memory footprint. Compared to conventional multi-read averaging for noise reduction, HD-PV and HARP achieve comparable accuracy with up to $6.1\times$ and $3.5\times$ lower latency and $6.2\times$ and $9.5\times$ better energy efficiency, respectively. To the best of our knowledge, this is the first application of Hadamard-encoded verification to RRAM WV.
format Preprint
id arxiv_https___arxiv_org_abs_2604_12420
institution arXiv
publishDate 2026
record_format arxiv
spellingShingle HARP: Hadamard-Domain Write-and-Verify for Noise-Robust RRAM Programming
Choi, Ilhuan
Yoo, Jiwon
Lee, Yoona
Jeong, Yewon
Lee, Jason Jaesung
Choi, Woo-Seok
Hardware Architecture
Write-and-verify (WV) is essential for programming multi-level RRAM weights, yet under scaled-voltage and low-SNR conditions the verify read increasingly limits mapping accuracy, convergence speed and energy. We propose a Hadamard-domain WV framework that improves verify reliability without adding analog hardware. % without introducing additional analog blocks % while leveraging the existing analog front-end \emph{HD-PV} (Hadamard-Encoded Parallel-Verify) replaces conventional one-hot verify reads with $N$ orthogonal Hadamard patterns for an $N$-cell column. Changing the read basis without increasing the column-level read count, inverse Hadamard decoding reduces uncorrelated read-noise variance by a factor of $N$ and cancels common-mode disturbances. \emph{HARP} (Hadamard-based ADC-Energy-Reduced Parallel-Verify) further exploits the fact that WV needs only ternary update decisions, not full digital codes, and replaces SAR conversions with lightweight compare-only operations. Across CIFAR-10, CIFAR-100, and keyword spotting under severe read noise, conventional WV loses over 20\,\% accuracy on CIFAR-10, while HD-PV and HARP limit the loss to 0.6\,\% and 1\,\% under the same memory footprint. Compared to conventional multi-read averaging for noise reduction, HD-PV and HARP achieve comparable accuracy with up to $6.1\times$ and $3.5\times$ lower latency and $6.2\times$ and $9.5\times$ better energy efficiency, respectively. To the best of our knowledge, this is the first application of Hadamard-encoded verification to RRAM WV.
title HARP: Hadamard-Domain Write-and-Verify for Noise-Robust RRAM Programming
topic Hardware Architecture
url https://arxiv.org/abs/2604.12420