CODO: An Automated Compiler for Comprehensive Dataflow Optimization
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arXiv
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| Main Authors: | , , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866914471291650048 |
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| author | Zhang, Weichuang Wang, Yiquan Zhang, Xinzhou Zhang, Chi Feng, Yu Hou, Xiaofeng Li, Chao Zhao, Jieru Guo, Minyi |
| author_facet | Zhang, Weichuang Wang, Yiquan Zhang, Xinzhou Zhang, Chi Feng, Yu Hou, Xiaofeng Li, Chao Zhao, Jieru Guo, Minyi |
| contents | FPGAs are well-suited for dataflow architectures that process data in a streaming or pipelined manner, thus satisfying the high computational and communication demands of emerging applications. However, manually implementing an efficient dataflow architecture for large-scale applications is still challenging, even for specialists who use high-level synthesis (HLS) to simplify FPGA programming.
To address this, we introduce CODO, an automated compiler that generates feasible and efficient dataflow accelerators on FPGAs. CODO features a systematic method for detecting and eliminating both coarse-grained and fine-grained dataflow violations. Building on this, CODO performs both on- and off-chip data movement optimizations to maximize transfer efficiency. To guarantee a higher design quality, CODO performs automatic scheduling to generate high-performance dataflow accelerators, ensuring a balanced performance-resource trade-off. Synthesis results show that CODO delivers $1.45\times$ to $4.52\times$ latency speedups on typical computation kernels and $3.7\times$ to $33.8\times$ speedups on DNN models compared to SOTA frameworks. In on-board evaluations, CODO achieves $7.3\times$ average speedup on CNN models and $2.07\times$ average speedup on the GPT-2 model over SOTA frameworks. The compiler is open-sourced at https://github.com/sjtu-zhao-lab/codo-artifact. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_12618 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | CODO: An Automated Compiler for Comprehensive Dataflow Optimization Zhang, Weichuang Wang, Yiquan Zhang, Xinzhou Zhang, Chi Feng, Yu Hou, Xiaofeng Li, Chao Zhao, Jieru Guo, Minyi Hardware Architecture FPGAs are well-suited for dataflow architectures that process data in a streaming or pipelined manner, thus satisfying the high computational and communication demands of emerging applications. However, manually implementing an efficient dataflow architecture for large-scale applications is still challenging, even for specialists who use high-level synthesis (HLS) to simplify FPGA programming. To address this, we introduce CODO, an automated compiler that generates feasible and efficient dataflow accelerators on FPGAs. CODO features a systematic method for detecting and eliminating both coarse-grained and fine-grained dataflow violations. Building on this, CODO performs both on- and off-chip data movement optimizations to maximize transfer efficiency. To guarantee a higher design quality, CODO performs automatic scheduling to generate high-performance dataflow accelerators, ensuring a balanced performance-resource trade-off. Synthesis results show that CODO delivers $1.45\times$ to $4.52\times$ latency speedups on typical computation kernels and $3.7\times$ to $33.8\times$ speedups on DNN models compared to SOTA frameworks. In on-board evaluations, CODO achieves $7.3\times$ average speedup on CNN models and $2.07\times$ average speedup on the GPT-2 model over SOTA frameworks. The compiler is open-sourced at https://github.com/sjtu-zhao-lab/codo-artifact. |
| title | CODO: An Automated Compiler for Comprehensive Dataflow Optimization |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.12618 |