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| Formato: | Preprint |
| Publicado: |
2026
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| Acceso en línea: | https://arxiv.org/abs/2604.12715 |
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| author | Mantovani, Filippo Banchelli, Fabio Vizcaino, Pablo Ferrer, Roger Palomar, Oscar Minervini, Francesco Labarta, Jesus Olivieri, Mauro Pomata, Sebastiano Marcuello, Pedro Cortina, Jordi Moreno, Alberto Sans, Josep Espasa, Roger Papaefstathiou, Vassilis Dimou, Nikolaos Ieronymakis, Georgios Psathakis, Antonis Giaourtas, Michalis Mastorakis, Iasonas Marazakis, Manolis Guthmuller, Eric Bocco, Andrea Fereyre, Jérôme Fuguet, César Kovač, Mate Kovač, Mario Mrković, Luka Ramljak, Josip Bertaccini, Luca Fischer, Tim Gurkaynak, Frank K. Scheffler, Paul Benini, Luca Goel, Bhavishya Manivannan, Madhavan Rocha, Tiago Neves, Nuno Krüger, Jens |
| author_facet | Mantovani, Filippo Banchelli, Fabio Vizcaino, Pablo Ferrer, Roger Palomar, Oscar Minervini, Francesco Labarta, Jesus Olivieri, Mauro Pomata, Sebastiano Marcuello, Pedro Cortina, Jordi Moreno, Alberto Sans, Josep Espasa, Roger Papaefstathiou, Vassilis Dimou, Nikolaos Ieronymakis, Georgios Psathakis, Antonis Giaourtas, Michalis Mastorakis, Iasonas Marazakis, Manolis Guthmuller, Eric Bocco, Andrea Fereyre, Jérôme Fuguet, César Kovač, Mate Kovač, Mario Mrković, Luka Ramljak, Josip Bertaccini, Luca Fischer, Tim Gurkaynak, Frank K. Scheffler, Paul Benini, Luca Goel, Bhavishya Manivannan, Madhavan Rocha, Tiago Neves, Nuno Krüger, Jens |
| contents | This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European HPC processor ecosystem. EPAC is implemented in GlobalFoundries 22FDX (GF22FDX) technology, covers an area of 27 sq mm with approximately 0.3 billion transistors, and integrates three distinct RISC-V compute tiles targeting different workload classes: VEC, a vector processing tile for double-precision HPC workloads; STX, a many-core tile optimized for stencil and machine learning computations; and VRP, a variable-precision tile for iterative numerical solvers requiring extended floating-point formats. All tiles are connected through a Coherent Hub Interface (CHI) based network-on-chip with a distributed L2 cache system and communicate with external memory via a SerDes link. The chip was taped out in GF22FDX technology and successfully brought up, with all major IP blocks validated. This paper describes the architecture of each tile and the uncore infrastructure, the integration and physical implementation process, and the board-level bring-up activities. It also reflects on the engineering and coordination lessons learned from a full chip design effort distributed across academic and industrial partners in Europe. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_12715 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | EPAC: The Last Dance Mantovani, Filippo Banchelli, Fabio Vizcaino, Pablo Ferrer, Roger Palomar, Oscar Minervini, Francesco Labarta, Jesus Olivieri, Mauro Pomata, Sebastiano Marcuello, Pedro Cortina, Jordi Moreno, Alberto Sans, Josep Espasa, Roger Papaefstathiou, Vassilis Dimou, Nikolaos Ieronymakis, Georgios Psathakis, Antonis Giaourtas, Michalis Mastorakis, Iasonas Marazakis, Manolis Guthmuller, Eric Bocco, Andrea Fereyre, Jérôme Fuguet, César Kovač, Mate Kovač, Mario Mrković, Luka Ramljak, Josip Bertaccini, Luca Fischer, Tim Gurkaynak, Frank K. Scheffler, Paul Benini, Luca Goel, Bhavishya Manivannan, Madhavan Rocha, Tiago Neves, Nuno Krüger, Jens Hardware Architecture Distributed, Parallel, and Cluster Computing This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European HPC processor ecosystem. EPAC is implemented in GlobalFoundries 22FDX (GF22FDX) technology, covers an area of 27 sq mm with approximately 0.3 billion transistors, and integrates three distinct RISC-V compute tiles targeting different workload classes: VEC, a vector processing tile for double-precision HPC workloads; STX, a many-core tile optimized for stencil and machine learning computations; and VRP, a variable-precision tile for iterative numerical solvers requiring extended floating-point formats. All tiles are connected through a Coherent Hub Interface (CHI) based network-on-chip with a distributed L2 cache system and communicate with external memory via a SerDes link. The chip was taped out in GF22FDX technology and successfully brought up, with all major IP blocks validated. This paper describes the architecture of each tile and the uncore infrastructure, the integration and physical implementation process, and the board-level bring-up activities. It also reflects on the engineering and coordination lessons learned from a full chip design effort distributed across academic and industrial partners in Europe. |
| title | EPAC: The Last Dance |
| topic | Hardware Architecture Distributed, Parallel, and Cluster Computing |
| url | https://arxiv.org/abs/2604.12715 |