Tensor Memory Engine: On-the-fly Data Reorganization for Ideal Locality
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arXiv
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| Autores principales: | , , , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866910130129338368 |
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| author | Hoornaert, Denis Strickler, Cole Athanassoulis, Manos Caccamo, Marco Yun, Heechul Mancuso, Renato |
| author_facet | Hoornaert, Denis Strickler, Cole Athanassoulis, Manos Caccamo, Marco Yun, Heechul Mancuso, Renato |
| contents | The shift to data-intensive processing from the cloud to the edge has introduced new challenges and expectations for the next generation of intelligent computing systems. As the memory wall continues to grow, modern systems can only meet these performance expectations by displaying data access patterns that exhibit ideal layouts in memory and ideal spatiotemporal locality in caches. However, only a few data-intensive applications are characterized by ideal locality. Instead, most applications exhibit either (i) poor locality when naively implemented and must undergo costly redesigns and tuning or (ii) inflated memory footprint to offer proper locality.
To address the aforementioned challenges, we propose a hardware/software co-designed approach that can be implemented on commercially available SoC/FPGA platforms. Our approach seamlessly inserts in the CPUs' data path a Tensor Memory Engine that provides data with an ideal cache locality to running applications by (i) accessing the memory on behalf of the CPUs and (ii) composing a re-organized view of the memory layout. Unlike in- and near-memory computing approaches, it sets itself apart by clearly decoupling computing and memory accesses; computation is still performed on CPUs while the data re-organization is delegated to the Tensor Memory Engine. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_13319 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Tensor Memory Engine: On-the-fly Data Reorganization for Ideal Locality Hoornaert, Denis Strickler, Cole Athanassoulis, Manos Caccamo, Marco Yun, Heechul Mancuso, Renato Hardware Architecture The shift to data-intensive processing from the cloud to the edge has introduced new challenges and expectations for the next generation of intelligent computing systems. As the memory wall continues to grow, modern systems can only meet these performance expectations by displaying data access patterns that exhibit ideal layouts in memory and ideal spatiotemporal locality in caches. However, only a few data-intensive applications are characterized by ideal locality. Instead, most applications exhibit either (i) poor locality when naively implemented and must undergo costly redesigns and tuning or (ii) inflated memory footprint to offer proper locality. To address the aforementioned challenges, we propose a hardware/software co-designed approach that can be implemented on commercially available SoC/FPGA platforms. Our approach seamlessly inserts in the CPUs' data path a Tensor Memory Engine that provides data with an ideal cache locality to running applications by (i) accessing the memory on behalf of the CPUs and (ii) composing a re-organized view of the memory layout. Unlike in- and near-memory computing approaches, it sets itself apart by clearly decoupling computing and memory accesses; computation is still performed on CPUs while the data re-organization is delegated to the Tensor Memory Engine. |
| title | Tensor Memory Engine: On-the-fly Data Reorganization for Ideal Locality |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.13319 |