An ASIC Emulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems
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arXiv
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866918448806756352 |
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| author | Gonul, Yilmaz Ege Taskin, Baris |
| author_facet | Gonul, Yilmaz Ege Taskin, Baris |
| contents | Oscillator-based Ising/Potts machines (OIMs/OPMs) are promising hardware accelerators for NP-hard combinatorial optimization problems using coupled oscillator synchronization dynamics. Analog OIMs/OPMs offer speed advantages but have limited coupling resolution, process variation susceptibility, and scalability issues, while digital GPU/CPU emulations provide flexibility but suffer from irregular memory access patterns and energy inefficiency. This work presents a custom ASIC architecture that digitally emulates OIM/OPM dynamics using simplified fixedpoint Kuramoto model equations. The scalable design features processing elements with direct interconnections, eliminating shared memory bottleneck while maintaining digital programmability and precision. A 20x20 processing element array with king's graph connectivity is prototyped and evaluated via post-layout simulations on unweighted/weighted max-cut and graph coloring problems, achieving 97-100% maximum accuracy with significant speed and energy improvements over general-purpose platforms, demonstrating the viability of algorithmically codesigned ASICs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_14027 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | An ASIC Emulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems Gonul, Yilmaz Ege Taskin, Baris Hardware Architecture Emerging Technologies Oscillator-based Ising/Potts machines (OIMs/OPMs) are promising hardware accelerators for NP-hard combinatorial optimization problems using coupled oscillator synchronization dynamics. Analog OIMs/OPMs offer speed advantages but have limited coupling resolution, process variation susceptibility, and scalability issues, while digital GPU/CPU emulations provide flexibility but suffer from irregular memory access patterns and energy inefficiency. This work presents a custom ASIC architecture that digitally emulates OIM/OPM dynamics using simplified fixedpoint Kuramoto model equations. The scalable design features processing elements with direct interconnections, eliminating shared memory bottleneck while maintaining digital programmability and precision. A 20x20 processing element array with king's graph connectivity is prototyped and evaluated via post-layout simulations on unweighted/weighted max-cut and graph coloring problems, achieving 97-100% maximum accuracy with significant speed and energy improvements over general-purpose platforms, demonstrating the viability of algorithmically codesigned ASICs. |
| title | An ASIC Emulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems |
| topic | Hardware Architecture Emerging Technologies |
| url | https://arxiv.org/abs/2604.14027 |