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| Main Authors: | , , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2604.14237 |
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| _version_ | 1866917411519725568 |
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| author | Song, Zhan Liu, Yu-Tung Chen, Chen Sun, Guoheng Yin, Jiaqi Ho, Chia-tung Li, Ang Ren, Haoxing Yu, Cunxi |
| author_facet | Song, Zhan Liu, Yu-Tung Chen, Chen Sun, Guoheng Yin, Jiaqi Ho, Chia-tung Li, Ang Ren, Haoxing Yu, Cunxi |
| contents | Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optimal topologies remains a persistent bottleneck, as conventional exhaustive search methods become computationally intractable with increasing circuit complexity in advanced nodes. This paper introduces TOPCELL, a novel and scalable framework that reformulates high-dimensional topology exploration as a generative task using Large Language Models (LLMs). We employ Group Relative Policy Optimization (GRPO) to fine-tune the model, aligning its topology optimization strategy with logical (circuit) and spatial (layout) constraints. Experimental results within an industrial flow targeting an advanced 2nm technology node demonstrate that TOPCELL significantly outperforms foundation models in discovering routable, physically-aware topologies. When integrated into a state-of-the-art (SOTA) automation flow for a 7nm library generation task, TOPCELL exhibits robust zero-shot generalization and matches the layout quality of exhaustive solvers while achieving an 85.91x speedup. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_14237 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | TOPCELL: Topology Optimization of Standard Cell via LLMs Song, Zhan Liu, Yu-Tung Chen, Chen Sun, Guoheng Yin, Jiaqi Ho, Chia-tung Li, Ang Ren, Haoxing Yu, Cunxi Machine Learning Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optimal topologies remains a persistent bottleneck, as conventional exhaustive search methods become computationally intractable with increasing circuit complexity in advanced nodes. This paper introduces TOPCELL, a novel and scalable framework that reformulates high-dimensional topology exploration as a generative task using Large Language Models (LLMs). We employ Group Relative Policy Optimization (GRPO) to fine-tune the model, aligning its topology optimization strategy with logical (circuit) and spatial (layout) constraints. Experimental results within an industrial flow targeting an advanced 2nm technology node demonstrate that TOPCELL significantly outperforms foundation models in discovering routable, physically-aware topologies. When integrated into a state-of-the-art (SOTA) automation flow for a 7nm library generation task, TOPCELL exhibits robust zero-shot generalization and matches the layout quality of exhaustive solvers while achieving an 85.91x speedup. |
| title | TOPCELL: Topology Optimization of Standard Cell via LLMs |
| topic | Machine Learning |
| url | https://arxiv.org/abs/2604.14237 |