CMOS-integrated superparamagnetic tunnel junction-based p-bit
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arXiv
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866915939498328064 |
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| author | Yoon, Ju-Young Cacoilo, Nuno Madhavan, Advait McClelland, Jabez J. Kanai, Shun Ohno, Hideo Fukami, Shunsuke Borders, William A. |
| author_facet | Yoon, Ju-Young Cacoilo, Nuno Madhavan, Advait McClelland, Jabez J. Kanai, Shun Ohno, Hideo Fukami, Shunsuke Borders, William A. |
| contents | Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_14446 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | CMOS-integrated superparamagnetic tunnel junction-based p-bit Yoon, Ju-Young Cacoilo, Nuno Madhavan, Advait McClelland, Jabez J. Kanai, Shun Ohno, Hideo Fukami, Shunsuke Borders, William A. Emerging Technologies Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications. |
| title | CMOS-integrated superparamagnetic tunnel junction-based p-bit |
| topic | Emerging Technologies |
| url | https://arxiv.org/abs/2604.14446 |