AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designs
Fuente:
arXiv
Saved in:
| Main Authors: | Nadimi, Bardia, Zheng, Hao |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Retrofitting Control Flow Graphs in LLVM IR for Auto Vectorization
by: Fang, Shihan, et al.
Published: (2025)
by: Fang, Shihan, et al.
Published: (2025)
Using LLM such as ChatGPT for Designing and Implementing a RISC Processor: Execution,Challenges and Limitations
by: Hossain, Shadeeb, et al.
Published: (2024)
by: Hossain, Shadeeb, et al.
Published: (2024)
A Vertically Integrated Framework for Templatized Chip Design
by: Kim, Jeongeun, et al.
Published: (2025)
by: Kim, Jeongeun, et al.
Published: (2025)
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
by: Nadimi, Bardia, et al.
Published: (2024)
by: Nadimi, Bardia, et al.
Published: (2024)
Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
by: Gai, Jiahao, et al.
Published: (2025)
by: Gai, Jiahao, et al.
Published: (2025)
AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs
by: Zhou, Xiaofeng, et al.
Published: (2026)
by: Zhou, Xiaofeng, et al.
Published: (2026)
KernelCraft: Benchmarking for Agentic Close-to-Metal Kernel Generation on Emerging Hardware
by: Nie, Jiayi, et al.
Published: (2026)
by: Nie, Jiayi, et al.
Published: (2026)
Inferring Message Flows From System Communication Traces
by: Nadimi, Bardia, et al.
Published: (2024)
by: Nadimi, Bardia, et al.
Published: (2024)
A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models
by: Guo, Cong, et al.
Published: (2024)
by: Guo, Cong, et al.
Published: (2024)
FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
by: Shih, Yu-An, et al.
Published: (2025)
by: Shih, Yu-An, et al.
Published: (2025)
David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
by: Shankar, Shashwat, et al.
Published: (2025)
by: Shankar, Shashwat, et al.
Published: (2025)
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
by: Nadimi, Bardia, et al.
Published: (2025)
by: Nadimi, Bardia, et al.
Published: (2025)
Testing Resource Isolation for System-on-Chip Architectures
by: Ledent, Philippe, et al.
Published: (2024)
by: Ledent, Philippe, et al.
Published: (2024)
QuArch: A Benchmark for Evaluating LLM Reasoning in Computer Architecture
by: Prakash, Shvetank, et al.
Published: (2025)
by: Prakash, Shvetank, et al.
Published: (2025)
Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing
by: Rostami, Mohamadreza, et al.
Published: (2024)
by: Rostami, Mohamadreza, et al.
Published: (2024)
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)
by: Collini, Luca, et al.
Published: (2024)
Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress)
by: Short, Benedict, et al.
Published: (2025)
by: Short, Benedict, et al.
Published: (2025)
Scalable Software Testing in Fast Virtual Platforms: Leveraging SystemC, QEMU and Containerization
by: Jünger, Lukas, et al.
Published: (2025)
by: Jünger, Lukas, et al.
Published: (2025)
EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
by: Zhu, Jiaying, et al.
Published: (2026)
by: Zhu, Jiaying, et al.
Published: (2026)
Pushing the Performance Envelope of DNN-based Recommendation Systems Inference on GPUs
by: Jain, Rishabh, et al.
Published: (2024)
by: Jain, Rishabh, et al.
Published: (2024)
Memory-Aware Partitioning of Machine Learning Applications for Optimal Energy Use in Batteryless Systems
by: Gomez, Andres, et al.
Published: (2021)
by: Gomez, Andres, et al.
Published: (2021)
ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions
by: Vavelidou, Ioanna, et al.
Published: (2026)
by: Vavelidou, Ioanna, et al.
Published: (2026)
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)
by: Ye, Junhao, et al.
Published: (2026)
Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
by: Armato, Antonino, et al.
Published: (2026)
by: Armato, Antonino, et al.
Published: (2026)
FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)
by: Li, Kezhi, et al.
Published: (2026)
LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
by: Miao, Mingkai, et al.
Published: (2026)
by: Miao, Mingkai, et al.
Published: (2026)
Using LLMs to Facilitate Formal Verification of RTL
by: Orenes-Vera, Marcelo, et al.
Published: (2023)
by: Orenes-Vera, Marcelo, et al.
Published: (2023)
Offloading Data Center Tax
by: Revankar, Akshay, et al.
Published: (2025)
by: Revankar, Akshay, et al.
Published: (2025)
MEIC: Re-thinking RTL Debug Automation using LLMs
by: Xu, Ke, et al.
Published: (2024)
by: Xu, Ke, et al.
Published: (2024)
A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2024)
by: Xu, Zhihao, et al.
Published: (2024)
Structural Mutation Based Differential Testing for FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2025)
by: Xu, Zhihao, et al.
Published: (2025)
CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation
by: Mi, Zhendong, et al.
Published: (2024)
by: Mi, Zhendong, et al.
Published: (2024)
Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms
by: Bosbach, Nils, et al.
Published: (2025)
by: Bosbach, Nils, et al.
Published: (2025)
FlowPlace: Flow Matching for Chip Placement
by: Xie, Peng, et al.
Published: (2026)
by: Xie, Peng, et al.
Published: (2026)
A Multi-Expert Large Language Model Architecture for Verilog Code Generation
by: Nadimi, Bardia, et al.
Published: (2024)
by: Nadimi, Bardia, et al.
Published: (2024)
DRCY: Agentic Hardware Design Reviews
by: Dumont, Kyle, et al.
Published: (2026)
by: Dumont, Kyle, et al.
Published: (2026)
Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Models
by: Sandal, Selim, et al.
Published: (2024)
by: Sandal, Selim, et al.
Published: (2024)
Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
by: Heakl, Ahmed, et al.
Published: (2025)
by: Heakl, Ahmed, et al.
Published: (2025)
VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation
by: Wei, Anjiang, et al.
Published: (2025)
by: Wei, Anjiang, et al.
Published: (2025)
DUET: Agentic Design Understanding via Experimentation and Testing
by: Smith, Gus Henry, et al.
Published: (2025)
by: Smith, Gus Henry, et al.
Published: (2025)
Similar Items
-
Retrofitting Control Flow Graphs in LLVM IR for Auto Vectorization
by: Fang, Shihan, et al.
Published: (2025) -
Using LLM such as ChatGPT for Designing and Implementing a RISC Processor: Execution,Challenges and Limitations
by: Hossain, Shadeeb, et al.
Published: (2024) -
A Vertically Integrated Framework for Templatized Chip Design
by: Kim, Jeongeun, et al.
Published: (2025) -
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
by: Nadimi, Bardia, et al.
Published: (2024) -
Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
by: Gai, Jiahao, et al.
Published: (2025)