Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation
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arXiv
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| Autori principali: | , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866911599283929088 |
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| author | Chen, Mu-Chi Huang, Po-Hsuan Kao, Yu-Hung Liu, Yen-Fu Hung, Yu-Kai Liang, Cheng Ho, Shao-Chun Tu, Chia-Heng Hung, Shih-Hao |
| author_facet | Chen, Mu-Chi Huang, Po-Hsuan Kao, Yu-Hung Liu, Yen-Fu Hung, Yu-Kai Liang, Cheng Ho, Shao-Chun Tu, Chia-Heng Hung, Shih-Hao |
| contents | Recent advances in large language models have improved code generation, but their use in hardware description languages is still limited. Moreover, training data and testbenches for these models are often scarce. This paper presents a workflow that uses multi-agent models to generate testbenches for high-quality fine-tuning data. By automating testbench creation, the fine-tuned model for the specification-to-Verilog task achieves performance comparable to state-of-the-art methods on the refined VerilogEval v2 benchmark while using less training data. This study provides a basis for future work on LLM-based HDL generation and automated verification. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_15388 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation Chen, Mu-Chi Huang, Po-Hsuan Kao, Yu-Hung Liu, Yen-Fu Hung, Yu-Kai Liang, Cheng Ho, Shao-Chun Tu, Chia-Heng Hung, Shih-Hao Hardware Architecture Artificial Intelligence I.2.2; I.2.6; I.2.7; J.6 Recent advances in large language models have improved code generation, but their use in hardware description languages is still limited. Moreover, training data and testbenches for these models are often scarce. This paper presents a workflow that uses multi-agent models to generate testbenches for high-quality fine-tuning data. By automating testbench creation, the fine-tuned model for the specification-to-Verilog task achieves performance comparable to state-of-the-art methods on the refined VerilogEval v2 benchmark while using less training data. This study provides a basis for future work on LLM-based HDL generation and automated verification. |
| title | Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation |
| topic | Hardware Architecture Artificial Intelligence I.2.2; I.2.6; I.2.7; J.6 |
| url | https://arxiv.org/abs/2604.15388 |