Cover Image

Secure Authentication in Wireless IoT: Hamming Code Assisted SRAM PUF as Device Fingerprint

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Lehn, Florian, Ahr, Pascal, Schotten, Hans D.
Format:	Preprint
Published:	2026
Subjects:	Cryptography and Security Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes
by: Porlapothula, Dilli Babu, et al.
Published: (2025)

PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability
by: Lyu, Ning, et al.
Published: (2026)

High-Security Hardware Module with PUF and Hybrid Cryptography for Data Security
by: Amael, Joshua Tito, et al.
Published: (2024)

PUFBind: PUF-Enabled Lightweight Program Binary Authentication for FPGA-based Embedded Systems
by: Swaroopa, Sneha, et al.
Published: (2025)

SAILOR: A Scalable and Energy-Efficient Ultra-Lightweight RISC-V for IoT Security
by: Ewert, Christian, et al.
Published: (2026)

CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing
by: Zhang, Jingyao, et al.
Published: (2025)

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
by: Ku, Jonathan, et al.
Published: (2024)

Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
by: Pham, Anh Kiet, et al.
Published: (2026)

Attack on a PUF-based Secure Binary Neural Network
by: Basak, Bijeet, et al.
Published: (2025)

PA-Boot: A Formally Verified Authentication Protocol for Multiprocessor Secure Boot
by: Zhang, Zhuoruo, et al.
Published: (2022)

LaMoS: Enabling Efficient Large Number Modular Multiplication through SRAM-based CiM Acceleration
by: Li, Haomin, et al.
Published: (2025)

RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
by: Mankali, Lakshmi Likhitha, et al.
Published: (2024)

WebGPU-SPY: Finding Fingerprints in the Sandbox through GPU Cache Attacks
by: Ferguson, Ethan, et al.
Published: (2024)

Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
by: Raj, Kshitij, et al.
Published: (2025)

Secure Scattered Memory: Rethinking Secure Enclave Memory with Secret Sharing
by: Geng, Haoran, et al.
Published: (2024)

Supporting Secured Integration of Microarchitectural Defenses
by: Ramkrishnan, Kartik, et al.
Published: (2026)

Formal Verification of Secure Encrypted Virtualization
by: Weerasena, Hansika, et al.
Published: (2026)

Security Properties for Open-Source Hardware Designs
by: Rogers, Jayden, et al.
Published: (2024)

An Early Experience with Confidential Computing Architecture for On-Device Model Protection
by: Abdollahi, Sina, et al.
Published: (2025)

On the Importance of Reproducibility of Experimental Results Especially in the Domain of Security
by: Petryk, Dmytro, et al.
Published: (2024)

Efficient and Lightweight In-memory Computing Architecture for Hardware Security
by: Ajmi, Hala, et al.
Published: (2022)

Modern Hardware Security: A Review of Attacks and Countermeasures
by: Mishra, Jyotiprakash, et al.
Published: (2025)

New Security Challenges Towards In-Sensor Computing Systems
by: Kajol, Mashrafi, et al.
Published: (2025)

REDACTOR: eFPGA Redaction for DNN Accelerator Security
by: Baddour, Yazan, et al.
Published: (2025)

GPU in the Blind Spot: Overlooked Security Risks in Transportation
by: Puspa, Sefatun-Noor, et al.
Published: (2025)

The Avatar Cache: Enabling On-Demand Security with Morphable Cache Architecture
by: Bhatla, Anubhav, et al.
Published: (2026)

MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker
by: Qureshi, Moinuddin, et al.
Published: (2024)

CIBPU: A Conflict-Invisible Secure Branch Prediction Unit
by: Zhou, Zhe, et al.
Published: (2025)

Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
by: Mulhem, Saleh, et al.
Published: (2024)

Fastrack: Fast IO for Secure ML using GPU TEEs
by: Wang, Yongqin, et al.
Published: (2024)

PoSyn: Secure Power Side-Channel Aware Synthesis
by: Srivastava, Amisha, et al.
Published: (2025)

FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption
by: Xu, Zhihan, et al.
Published: (2025)

MOAT: Securely Mitigating Rowhammer with Per-Row Activation Counters
by: Qureshi, Moinuddin, et al.
Published: (2024)

Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of Deep Neural Networks
by: Lin, Ning, et al.
Published: (2024)

AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures
by: Fu, Bo, et al.
Published: (2025)

RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective
by: Pinto, Sandro, et al.
Published: (2024)

ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes
by: Kvalsvik, Amund Bergland, et al.
Published: (2025)

SecScale: A Scalable and Secure Trusted Execution Environment for Servers
by: Sunny, Ani, et al.
Published: (2024)

Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies
by: Luo, Haocong, et al.
Published: (2025)

Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance
by: Canpolat, Oğuzhan, et al.
Published: (2025)