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| Main Authors: | , , , , , , , , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2604.16007 |
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| _version_ | 1866918452420149248 |
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| author | Wu, Haoran Cao, Zeyu Lai, Yao Lou, Binglei Nie, Jiayi Xiao, Can Adeniran, Timi Forys, Przemyslaw Johar, Kauser Wright, Catriona Liu, Junyi Shi, Kai Lane, Nicholas D. Antonova, Rika Cheng, Jianyi Jones, Timothy Zhao, Aaron Mullins, Robert |
| author_facet | Wu, Haoran Cao, Zeyu Lai, Yao Lou, Binglei Nie, Jiayi Xiao, Can Adeniran, Timi Forys, Przemyslaw Johar, Kauser Wright, Catriona Liu, Junyi Shi, Kai Lane, Nicholas D. Antonova, Rika Cheng, Jianyi Jones, Timothy Zhao, Aaron Mullins, Robert |
| contents | Emerging agentic LLM workloads are driving rapidly growing demand on both memory capacity and bandwidth, with different phases of inference (e.g., prefill and decode) imposing distinct requirements. Industry is responding by composing heterogeneous accelerators into single interconnected systems, as exemplified by NVIDIA's Vera Rubin platform, where each device brings its own memory architecture.
This heterogeneity is further compounded by a widening landscape of available memory technologies: high-density on-chip SRAM, HBM, LPDDR, GDDR, and emerging options such as high-bandwidth flash (HBF), each offering different capacity, bandwidth, and power trade-offs.
Identifying the right memory architecture for next-generation inference accelerators requires navigating a vast and rapidly evolving design space, in which the interplay between workload characteristics, NPU design dimensions, and memory system design remains largely underexplored.
To address this challenge, we present MemExplorer, a new memory system synthesizer for heterogeneous NPU systems. MemExplorer provides a unified abstraction for modeling diverse memory technologies across different hierarchy levels (e.g., on-chip and off-chip) and automatically determines an efficient heterogeneous memory system together with NPU design choices (e.g., matrix engine size) to balance throughput and power between prefilling and decoding devices in a multi-device NPU system.
Experimental results show that, under the same power budget for agentic workloads, MemExplorer achieves up to 2.3x higher energy efficiency than the baseline NPU and 3.23x higher than H100 in the prefill-only setting. Under equivalent performance targets in the decode setting, it further delivers up to 1.93x and 2.72x higher power efficiency over the baseline NPU and H100, respectively. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_16007 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | MemExplorer: Navigating the Heterogeneous Memory Design Space for Agentic Inference NPUs Wu, Haoran Cao, Zeyu Lai, Yao Lou, Binglei Nie, Jiayi Xiao, Can Adeniran, Timi Forys, Przemyslaw Johar, Kauser Wright, Catriona Liu, Junyi Shi, Kai Lane, Nicholas D. Antonova, Rika Cheng, Jianyi Jones, Timothy Zhao, Aaron Mullins, Robert Hardware Architecture Emerging agentic LLM workloads are driving rapidly growing demand on both memory capacity and bandwidth, with different phases of inference (e.g., prefill and decode) imposing distinct requirements. Industry is responding by composing heterogeneous accelerators into single interconnected systems, as exemplified by NVIDIA's Vera Rubin platform, where each device brings its own memory architecture. This heterogeneity is further compounded by a widening landscape of available memory technologies: high-density on-chip SRAM, HBM, LPDDR, GDDR, and emerging options such as high-bandwidth flash (HBF), each offering different capacity, bandwidth, and power trade-offs. Identifying the right memory architecture for next-generation inference accelerators requires navigating a vast and rapidly evolving design space, in which the interplay between workload characteristics, NPU design dimensions, and memory system design remains largely underexplored. To address this challenge, we present MemExplorer, a new memory system synthesizer for heterogeneous NPU systems. MemExplorer provides a unified abstraction for modeling diverse memory technologies across different hierarchy levels (e.g., on-chip and off-chip) and automatically determines an efficient heterogeneous memory system together with NPU design choices (e.g., matrix engine size) to balance throughput and power between prefilling and decoding devices in a multi-device NPU system. Experimental results show that, under the same power budget for agentic workloads, MemExplorer achieves up to 2.3x higher energy efficiency than the baseline NPU and 3.23x higher than H100 in the prefill-only setting. Under equivalent performance targets in the decode setting, it further delivers up to 1.93x and 2.72x higher power efficiency over the baseline NPU and H100, respectively. |
| title | MemExplorer: Navigating the Heterogeneous Memory Design Space for Agentic Inference NPUs |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.16007 |