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| Autores principales: | , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| Materias: | |
| Acceso en línea: | https://arxiv.org/abs/2604.16253 |
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| _version_ | 1866914483903922176 |
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| author | Wu, Jinyuan Wang, Michael Gong, Datao |
| author_facet | Wu, Jinyuan Wang, Michael Gong, Datao |
| contents | A clustering functional block implemented in field-programable-gate-array (FPGA) for time projection chambers (TPC) operating with predictable time regardless the complexity of the event is described in this paper. The clustering functional block reorganizes input data and the hits data belonging to the same clusters are output together for further process in the later stages. The clustering operation consists of two phases, data filling phase and data outputting phase, and the later uses the same number of clock cycles as the data filling phase. The clustering block can accommodate events with arbitrary number of clusters and number of hits per cluster as long as the total number of hits is within a predesigned limit. The operation time is exactly twice of the data filling time with no residual O(n2) term. The clustering block has been implemented with operating frequency of 200 MHz in a low-cost FPGA evaluation module and test results confirm the expected performance. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_16253 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | A Complexity Agnostic Clustering Engine for Time Projection Chambers and its Implementation in FPGA Wu, Jinyuan Wang, Michael Gong, Datao Instrumentation and Detectors A clustering functional block implemented in field-programable-gate-array (FPGA) for time projection chambers (TPC) operating with predictable time regardless the complexity of the event is described in this paper. The clustering functional block reorganizes input data and the hits data belonging to the same clusters are output together for further process in the later stages. The clustering operation consists of two phases, data filling phase and data outputting phase, and the later uses the same number of clock cycles as the data filling phase. The clustering block can accommodate events with arbitrary number of clusters and number of hits per cluster as long as the total number of hits is within a predesigned limit. The operation time is exactly twice of the data filling time with no residual O(n2) term. The clustering block has been implemented with operating frequency of 200 MHz in a low-cost FPGA evaluation module and test results confirm the expected performance. |
| title | A Complexity Agnostic Clustering Engine for Time Projection Chambers and its Implementation in FPGA |
| topic | Instrumentation and Detectors |
| url | https://arxiv.org/abs/2604.16253 |