E2AFS: Energy-Efficient Approximate Floating Point Square Rooter for Error Tolerant Computing
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arXiv
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| Autori principali: | , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866914486467690496 |
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| author | Goyal, Prateek Mothe, Jatin Kumar Reddy Shelke, Swara Rajesh Sahoo, Sujit Kumar |
| author_facet | Goyal, Prateek Mothe, Jatin Kumar Reddy Shelke, Swara Rajesh Sahoo, Sujit Kumar |
| contents | Floating-point square-root computation is a power- and delay-critical operation in edge-AI, signal-processing, and embedded systems. Conventional implementations typically rely on multipliers or iterative pipelines, resulting in increased hardware complexity, switching activity, and energy consumption. This work presents E2AFS, a lightweight and fully multiplier-free floating-point square-root architecture optimized for energy-efficient computation. By reducing logic depth and minimizing switching activity, the proposed design achieves substantial improvements in hardware efficiency and performance. FPGA implementation on an Artix-7 device demonstrates that E2AFS achieves the lowest dynamic power (7.63 mW), the shortest critical-path delay (4.639 ns), and the minimum power-delay product (35.39 pJ) compared to existing ESAS and CWAHA architectures. Error evaluation using multiple accuracy metrics, together with graphical analysis, shows that E2AFS closely approximates the exact square-root function with consistently low deviation. Application-level validation in Sobel edge detection and K-means color quantization further confirms its suitability for low-power real-time edge and embedded platforms. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_16964 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | E2AFS: Energy-Efficient Approximate Floating Point Square Rooter for Error Tolerant Computing Goyal, Prateek Mothe, Jatin Kumar Reddy Shelke, Swara Rajesh Sahoo, Sujit Kumar Hardware Architecture Floating-point square-root computation is a power- and delay-critical operation in edge-AI, signal-processing, and embedded systems. Conventional implementations typically rely on multipliers or iterative pipelines, resulting in increased hardware complexity, switching activity, and energy consumption. This work presents E2AFS, a lightweight and fully multiplier-free floating-point square-root architecture optimized for energy-efficient computation. By reducing logic depth and minimizing switching activity, the proposed design achieves substantial improvements in hardware efficiency and performance. FPGA implementation on an Artix-7 device demonstrates that E2AFS achieves the lowest dynamic power (7.63 mW), the shortest critical-path delay (4.639 ns), and the minimum power-delay product (35.39 pJ) compared to existing ESAS and CWAHA architectures. Error evaluation using multiple accuracy metrics, together with graphical analysis, shows that E2AFS closely approximates the exact square-root function with consistently low deviation. Application-level validation in Sobel edge detection and K-means color quantization further confirms its suitability for low-power real-time edge and embedded platforms. |
| title | E2AFS: Energy-Efficient Approximate Floating Point Square Rooter for Error Tolerant Computing |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.16964 |