Cover Image

Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Shao, Minghao, Wang, Zeng, Fu, Weimin, Guo, Xiaolong, Knechtel, Johann, Sinanoglu, Ozgur, Karri, Ramesh, Shafique, Muhammad
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
by: Fu, Weimin, et al.
Published: (2026)

From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
by: Fu, Weimin, et al.
Published: (2026)

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
by: Knechtel, Johann, et al.
Published: (2026)

TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
by: Sreekumar, Saideep, et al.
Published: (2026)

VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
by: Wang, Zeng, et al.
Published: (2025)

RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
by: Mankali, Lakshmi Likhitha, et al.
Published: (2024)

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
by: Wang, Zeng, et al.
Published: (2025)

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
by: Wang, Zeng, et al.
Published: (2024)

VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
by: Roy, Prithwish Basu, et al.
Published: (2026)

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
by: Bhandari, Jitendra, et al.
Published: (2024)

TrojanLoC: LLM-based Framework for RTL Trojan Localization
by: Xiao, Weihua, et al.
Published: (2025)

NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration
by: Wang, Zeng, et al.
Published: (2025)

HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking
by: Wang, Zeng, et al.
Published: (2026)

Targeted Wearout Attacks in Microprocessor Cores
by: Mashburn, Joshua, et al.
Published: (2025)

Large Language Models (LLMs) for Electronic Design Automation (EDA)
by: Xu, Kangwei, et al.
Published: (2025)

VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization
by: Wang, Zeng, et al.
Published: (2025)

Logic Encryption: This Time for Real
by: Karn, Rupesh Raj, et al.
Published: (2025)

SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design
by: Wang, Zeng, et al.
Published: (2025)

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)

C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
by: Collini, Luca, et al.
Published: (2024)

LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMs
by: Saha, Akashdeep, et al.
Published: (2025)

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)

LLM4PQC - Accurate and Efficient Synthesis of PQC Cores by Feedback-Driven LLMs
by: Perera, Buddhi, et al.
Published: (2026)

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
by: Wang, Fangzhou, et al.
Published: (2024)

Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
by: DeLorenzo, Matthew, et al.
Published: (2024)

ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
by: Deng, Chenhui, et al.
Published: (2026)

UVLLM: An Automated Universal RTL Verification Framework using LLMs
by: Hu, Yuchen, et al.
Published: (2024)

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
by: Allam, Ahmed, et al.
Published: (2024)

Lightweight Countermeasures Against Static Power Side-Channel Attacks
by: Bhandari, Jitendra, et al.
Published: (2024)

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)

Using LLMs to Facilitate Formal Verification of RTL
by: Orenes-Vera, Marcelo, et al.
Published: (2023)

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
by: Deng, Chenhui, et al.
Published: (2025)

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
by: Liu, Shang, et al.
Published: (2023)

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)

From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)

FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)

DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs
by: Akyash, Mohammad, et al.
Published: (2025)

SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions
by: Bhandari, Jitendra, et al.
Published: (2024)

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
by: Machetti, Simone, et al.
Published: (2025)