AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
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arXiv
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| Autores principales: | , , , , , , , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866910146747170816 |
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| author | Xue, Chenhao Wang, Yukun Guo, An Shi, Yuhui Zhou, Jinwei Dong, Xiping Yin, Yihan Zhang, Yuanpeng Jia, Tianyu Gao, Wei Wu, Qiang Si, Xin Yang, Jun Sun, Guangyu |
| author_facet | Xue, Chenhao Wang, Yukun Guo, An Shi, Yuhui Zhou, Jinwei Dong, Xiping Yin, Yihan Zhang, Yuanpeng Jia, Tianyu Gao, Wei Wu, Qiang Si, Xin Yang, Jun Sun, Guangyu |
| contents | SRAM-based compute-in-memory (CIM) offers high computational density and energy efficiency for deep neural network (DNN) accelerators, but its limited capacity causes on/off-chip data movement overhead for large DNN models. Existing CIM accelerator studies typically assume that DNN models fit entirely on-chip, leaving efficient dataflow design largely untapped. This paper introduces AccelCIM, a systematic dataflow exploration framework for SRAM CIM accelerator, which addresses two key limitations of prior work. (1) It formulates a systematic dataflow design space spanning CIM macro configurations and macro-array organizations. (2) It introduces rigorous design evaluation using cycle-accurate architectural simulation and post-layout PPA analysis. We conduct an extensive design space exploration and apply AccelCIM to representative LLM applications, providing practical insights for the principled design of CIM accelerators. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_17692 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator Xue, Chenhao Wang, Yukun Guo, An Shi, Yuhui Zhou, Jinwei Dong, Xiping Yin, Yihan Zhang, Yuanpeng Jia, Tianyu Gao, Wei Wu, Qiang Si, Xin Yang, Jun Sun, Guangyu Hardware Architecture SRAM-based compute-in-memory (CIM) offers high computational density and energy efficiency for deep neural network (DNN) accelerators, but its limited capacity causes on/off-chip data movement overhead for large DNN models. Existing CIM accelerator studies typically assume that DNN models fit entirely on-chip, leaving efficient dataflow design largely untapped. This paper introduces AccelCIM, a systematic dataflow exploration framework for SRAM CIM accelerator, which addresses two key limitations of prior work. (1) It formulates a systematic dataflow design space spanning CIM macro configurations and macro-array organizations. (2) It introduces rigorous design evaluation using cycle-accurate architectural simulation and post-layout PPA analysis. We conduct an extensive design space exploration and apply AccelCIM to representative LLM applications, providing practical insights for the principled design of CIM accelerators. |
| title | AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2604.17692 |