Enabling AI ASICs for Zero Knowledge Proof
Fuente:
arXiv
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| Autori principali: | , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866917420871974912 |
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| author | Tong, Jianming Dang, Jingtian Langowski, Simon Huang, Tianhao Ali, Asra Kun, Jeremy Jiang, Jevin Devadas, Srinivas Krishna, Tushar |
| author_facet | Tong, Jianming Dang, Jingtian Langowski, Simon Huang, Tianhao Ali, Asra Kun, Jeremy Jiang, Jevin Devadas, Srinivas Krishna, Tushar |
| contents | Zero-knowledge proof (ZKP) provers remain costly because multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs) dominate runtime as they need significant computation. AI ASICs such as TPUs provide massive matrix throughput and SotA energy efficiency. We present MORPH, the first framework that reformulates ZKP kernels to match AI-ASIC execution. We introduce Big-T complexity, a hardware-aware complexity model that exposes heterogeneous bottlenecks and layout-transformation costs ignored by Big-O. Guided by this analysis, (1) at arithmetic level, MORPH develops an MXU-centric extended-RNS lazy reduction that converts high-precision modular arithmetic into dense low-precision GEMMs, eliminating all carry chains, and (2) at dataflow level, MORPH constructs a unified-sharding layout-stationary TPU Pippenger MSM and optimized 3/5-step NTT that avoid on-TPU shuffles to minimize costly memory reorganization. Implemented in JAX, MORPH enables TPUv6e8 to achieve up-to 10x higher throughput on NTT and comparable throughput on MSM than GZKP. Our code: https://github.com/EfficientPPML/MORPH. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_17808 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Enabling AI ASICs for Zero Knowledge Proof Tong, Jianming Dang, Jingtian Langowski, Simon Huang, Tianhao Ali, Asra Kun, Jeremy Jiang, Jevin Devadas, Srinivas Krishna, Tushar Hardware Architecture Computation and Language Cryptography and Security Data Structures and Algorithms Programming Languages Zero-knowledge proof (ZKP) provers remain costly because multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs) dominate runtime as they need significant computation. AI ASICs such as TPUs provide massive matrix throughput and SotA energy efficiency. We present MORPH, the first framework that reformulates ZKP kernels to match AI-ASIC execution. We introduce Big-T complexity, a hardware-aware complexity model that exposes heterogeneous bottlenecks and layout-transformation costs ignored by Big-O. Guided by this analysis, (1) at arithmetic level, MORPH develops an MXU-centric extended-RNS lazy reduction that converts high-precision modular arithmetic into dense low-precision GEMMs, eliminating all carry chains, and (2) at dataflow level, MORPH constructs a unified-sharding layout-stationary TPU Pippenger MSM and optimized 3/5-step NTT that avoid on-TPU shuffles to minimize costly memory reorganization. Implemented in JAX, MORPH enables TPUv6e8 to achieve up-to 10x higher throughput on NTT and comparable throughput on MSM than GZKP. Our code: https://github.com/EfficientPPML/MORPH. |
| title | Enabling AI ASICs for Zero Knowledge Proof |
| topic | Hardware Architecture Computation and Language Cryptography and Security Data Structures and Algorithms Programming Languages |
| url | https://arxiv.org/abs/2604.17808 |