PVAC: A RowHammer Mitigation Architecture Exploiting Per-victim-row Counting
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arXiv
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| Autori principali: | , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866915949227016192 |
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| author | Kim, Jumin Baek, Seungmin Nam, Hwayong Wi, Minbok Kim, Nam Sung Ahn, Jung Ho |
| author_facet | Kim, Jumin Baek, Seungmin Nam, Hwayong Wi, Minbok Kim, Nam Sung Ahn, Jung Ho |
| contents | As DRAM scaling exacerbates RowHammer, DDR5 introduces per-row activation counting (PRAC) to track aggressor activity. However, PRAC indiscriminately increments counters on every activation -- including benign refreshes -- while relying solely on explicit RFM operations for resets. Consequently, counters saturate even in an idle bank, triggering cascading mitigations and degrading performance. This vulnerability arises from a fundamental mismatch: PRAC tracks the aggressor but aims to protect the victim.
We present Per-Victim-row hAmmered Counting (PVAC), a victim-based counting mechanism that aligns the counter semantics with the physical disturbance mechanism of RowHammer. PVAC increments the counters of victim rows, resets the activated row, and naturally bounds counter values under normal refresh. To enable efficient victim-based updates, PVAC employs a dedicated counter subarray (CSA) that performs all counter resets and increments concurrently with normal accesses, without timing overhead. We further devise an energy-efficient CSA layout that minimizes refresh-induced counter accesses. Through victim-based counting, PVAC supports higher hammering tolerance than PRAC while maintaining the same worst-case safety guarantee. Across benign workloads and adversarial attack patterns, PVAC avoids spurious Alerts, eliminates PRAC timing penalties, and achieves higher performance and lower energy consumption than prior PRAC-based defenses. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_20576 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | PVAC: A RowHammer Mitigation Architecture Exploiting Per-victim-row Counting Kim, Jumin Baek, Seungmin Nam, Hwayong Wi, Minbok Kim, Nam Sung Ahn, Jung Ho Cryptography and Security Hardware Architecture As DRAM scaling exacerbates RowHammer, DDR5 introduces per-row activation counting (PRAC) to track aggressor activity. However, PRAC indiscriminately increments counters on every activation -- including benign refreshes -- while relying solely on explicit RFM operations for resets. Consequently, counters saturate even in an idle bank, triggering cascading mitigations and degrading performance. This vulnerability arises from a fundamental mismatch: PRAC tracks the aggressor but aims to protect the victim. We present Per-Victim-row hAmmered Counting (PVAC), a victim-based counting mechanism that aligns the counter semantics with the physical disturbance mechanism of RowHammer. PVAC increments the counters of victim rows, resets the activated row, and naturally bounds counter values under normal refresh. To enable efficient victim-based updates, PVAC employs a dedicated counter subarray (CSA) that performs all counter resets and increments concurrently with normal accesses, without timing overhead. We further devise an energy-efficient CSA layout that minimizes refresh-induced counter accesses. Through victim-based counting, PVAC supports higher hammering tolerance than PRAC while maintaining the same worst-case safety guarantee. Across benign workloads and adversarial attack patterns, PVAC avoids spurious Alerts, eliminates PRAC timing penalties, and achieves higher performance and lower energy consumption than prior PRAC-based defenses. |
| title | PVAC: A RowHammer Mitigation Architecture Exploiting Per-victim-row Counting |
| topic | Cryptography and Security Hardware Architecture |
| url | https://arxiv.org/abs/2604.20576 |