An Efficient Wireless iBCI Headstage with Adaptive ADC Sample Rate
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
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2026
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| _version_ | 1866915954287443968 |
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| author | Liu, Hongyao Wang, Junyi Chen, Jinglong Zhai, Liuqun |
| author_facet | Liu, Hongyao Wang, Junyi Chen, Jinglong Zhai, Liuqun |
| contents | Implantable Brain-Computer Interfaces (iBCIs) are increasingly pivotal in clinical and daily applications. However, wireless iBCIs face severe constraints in power consumption and data throughput. To mitigate these bottlenecks, we propose a wireless iBCI headstage featuring adaptive ADC sampling and spike detection. Distinguishing our design from traditional application-layer compression, we employ a server-driven architecture that achieves source-level efficiency. Specifically, the server learns an optimal, electrode-specific sample rate vector to dynamically reconfigure the ADC hardware. This strategy reduces data volume directly at the acquisition layer (ADC and amplifier) rather than relying on computationally intensive post-digitization processing. Extensive experiments across diverse subjects and arrays demonstrate a power reduction of up to 40 mW and a 3.2x decrease in FPGA resource utilization, all while maintaining or exceeding decoding accuracy in both motor and visual tasks. This design offers a highly practical solution for long-term in-vivo recording. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_21247 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | An Efficient Wireless iBCI Headstage with Adaptive ADC Sample Rate Liu, Hongyao Wang, Junyi Chen, Jinglong Zhai, Liuqun Networking and Internet Architecture Performance Implantable Brain-Computer Interfaces (iBCIs) are increasingly pivotal in clinical and daily applications. However, wireless iBCIs face severe constraints in power consumption and data throughput. To mitigate these bottlenecks, we propose a wireless iBCI headstage featuring adaptive ADC sampling and spike detection. Distinguishing our design from traditional application-layer compression, we employ a server-driven architecture that achieves source-level efficiency. Specifically, the server learns an optimal, electrode-specific sample rate vector to dynamically reconfigure the ADC hardware. This strategy reduces data volume directly at the acquisition layer (ADC and amplifier) rather than relying on computationally intensive post-digitization processing. Extensive experiments across diverse subjects and arrays demonstrate a power reduction of up to 40 mW and a 3.2x decrease in FPGA resource utilization, all while maintaining or exceeding decoding accuracy in both motor and visual tasks. This design offers a highly practical solution for long-term in-vivo recording. |
| title | An Efficient Wireless iBCI Headstage with Adaptive ADC Sample Rate |
| topic | Networking and Internet Architecture Performance |
| url | https://arxiv.org/abs/2604.21247 |