SPAC: Automating FPGA-based Network Switches with Protocol Adaptive Customization
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arXiv
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| Autores principales: | , , , , , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866911618789539840 |
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| author | Li, Guoyu Cao, Yang Ng, Lucas H L Charlton, Alexander Wang, Qianzhou Punter, Will Papaphilippou, Philippos Guo, Ce Fan, Hongxiang Luk, Wayne Amarasinghe, Saman Brahmakshatriya, Ajay |
| author_facet | Li, Guoyu Cao, Yang Ng, Lucas H L Charlton, Alexander Wang, Qianzhou Punter, Will Papaphilippou, Philippos Guo, Ce Fan, Hongxiang Luk, Wayne Amarasinghe, Saman Brahmakshatriya, Ajay |
| contents | With network requirements diverging across emerging applications, latency-critical services demand minimal logic delay, while hyperscale training and collectives require sustained line-rate throughput for synchronized bulk transfers. This divergence creates an urgent need for custom network switches tailored to specialized protocols and application-specific traffic patterns. This paper presents SPAC (Switch and Protocol Adaptive Customization), a novel approach that automates the generation of FPGA-based network switches co-optimized for custom protocols and application-specific traffic patterns. SPAC introduces a unified workflow with a domain-specific language (DSL) for protocol-architecture co-design, a library of modular HLS-based adaptive switch components, and a trace-aware Design Space Exploration (DSE) engine. By providing a multi-fidelity simulation stack, SPAC enables rapid identification of Pareto-optimal designs prior to deployment. We demonstrate the efficacy of the domain-specific adaptation of SPAC across a spectrum of real-world scenarios, spanning from latency-sensitive sensor and HFT networks to hyperscale datacenter fabrics. Experimental results show that by tailoring the micro-architecture and protocol to the specific workload, SPAC-generated designs reduce LUT and BRAM usage by 55% and 53%, respectively. Compared to fixed-architecture counterparts, SPAC delivers latency reductions ranging from 7.8% to 38.4% across various tasks while maintaining adequate resource consumption and packet drop rate. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_21881 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | SPAC: Automating FPGA-based Network Switches with Protocol Adaptive Customization Li, Guoyu Cao, Yang Ng, Lucas H L Charlton, Alexander Wang, Qianzhou Punter, Will Papaphilippou, Philippos Guo, Ce Fan, Hongxiang Luk, Wayne Amarasinghe, Saman Brahmakshatriya, Ajay Networking and Internet Architecture Hardware Architecture With network requirements diverging across emerging applications, latency-critical services demand minimal logic delay, while hyperscale training and collectives require sustained line-rate throughput for synchronized bulk transfers. This divergence creates an urgent need for custom network switches tailored to specialized protocols and application-specific traffic patterns. This paper presents SPAC (Switch and Protocol Adaptive Customization), a novel approach that automates the generation of FPGA-based network switches co-optimized for custom protocols and application-specific traffic patterns. SPAC introduces a unified workflow with a domain-specific language (DSL) for protocol-architecture co-design, a library of modular HLS-based adaptive switch components, and a trace-aware Design Space Exploration (DSE) engine. By providing a multi-fidelity simulation stack, SPAC enables rapid identification of Pareto-optimal designs prior to deployment. We demonstrate the efficacy of the domain-specific adaptation of SPAC across a spectrum of real-world scenarios, spanning from latency-sensitive sensor and HFT networks to hyperscale datacenter fabrics. Experimental results show that by tailoring the micro-architecture and protocol to the specific workload, SPAC-generated designs reduce LUT and BRAM usage by 55% and 53%, respectively. Compared to fixed-architecture counterparts, SPAC delivers latency reductions ranging from 7.8% to 38.4% across various tasks while maintaining adequate resource consumption and packet drop rate. |
| title | SPAC: Automating FPGA-based Network Switches with Protocol Adaptive Customization |
| topic | Networking and Internet Architecture Hardware Architecture |
| url | https://arxiv.org/abs/2604.21881 |