HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference
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arXiv
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| Autori principali: | , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866915954602016768 |
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| author | Sun, Chang Que, Zhiqiang Zadeh, Bakhtiar Liu, Qibin Alvarez, Kevin H. Luk, Wayne Spiropulu, Maria |
| author_facet | Sun, Chang Que, Zhiqiang Zadeh, Bakhtiar Liu, Qibin Alvarez, Kevin H. Luk, Wayne Spiropulu, Maria |
| contents | Lookup-table (LUT) based neural networks can deliver ultra-low latency and excellent hardware efficiency on FPGAs by mapping arithmetic operations directly onto the logic primitives. However, state-of-the-art LUT-aware training (LAT) approaches remain difficult to use in practice: they are often orders of magnitude slower to train than conventional networks, require non-trivial manual tuning for hardware efficiency, and lack an end-to-end workflow. This work presents HGQ-LUT, integrated in https://github.com/calad0i/HGQ2, a new LAT approach that achieves state-of-the-art hardware efficiency while accelerating training by over 100 times on modern GPUs. HGQ-LUT introduces LUT-Dense and LUT-Conv layers that are implemented with regular, accelerator-efficient tensor operations during training, which are then compiled into logic LUTs for hardware. By combining these layers with fine-grained, element-wise heterogeneous quantization (including zero-bit pruning) and a LUT-aware resource surrogate, HGQ-LUT enables the automatic exploration of accuracy-resource trade-offs without manual bit-width tuning. We further integrate HGQ-LUT into open-source toolchains, enabling unified design, compilation, and bit-exact verification of hybrid architectures that mix LUT-based with conventional arithmetic blocks. These features make LAT-based DNNs practical for real-world deployment, such as at the CERN Large Hadron Collider's experiments. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2604_22293 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference Sun, Chang Que, Zhiqiang Zadeh, Bakhtiar Liu, Qibin Alvarez, Kevin H. Luk, Wayne Spiropulu, Maria Hardware Architecture Machine Learning High Energy Physics - Experiment Lookup-table (LUT) based neural networks can deliver ultra-low latency and excellent hardware efficiency on FPGAs by mapping arithmetic operations directly onto the logic primitives. However, state-of-the-art LUT-aware training (LAT) approaches remain difficult to use in practice: they are often orders of magnitude slower to train than conventional networks, require non-trivial manual tuning for hardware efficiency, and lack an end-to-end workflow. This work presents HGQ-LUT, integrated in https://github.com/calad0i/HGQ2, a new LAT approach that achieves state-of-the-art hardware efficiency while accelerating training by over 100 times on modern GPUs. HGQ-LUT introduces LUT-Dense and LUT-Conv layers that are implemented with regular, accelerator-efficient tensor operations during training, which are then compiled into logic LUTs for hardware. By combining these layers with fine-grained, element-wise heterogeneous quantization (including zero-bit pruning) and a LUT-aware resource surrogate, HGQ-LUT enables the automatic exploration of accuracy-resource trade-offs without manual bit-width tuning. We further integrate HGQ-LUT into open-source toolchains, enabling unified design, compilation, and bit-exact verification of hybrid architectures that mix LUT-based with conventional arithmetic blocks. These features make LAT-based DNNs practical for real-world deployment, such as at the CERN Large Hadron Collider's experiments. |
| title | HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference |
| topic | Hardware Architecture Machine Learning High Energy Physics - Experiment |
| url | https://arxiv.org/abs/2604.22293 |