TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog

Fuente: arXiv

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Bibliographic Details
Main Authors:	Abdollahi, Armin, Ashrafi, Negin, Kamal, Mehdi, Pedram, Massoud
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Machine Learning
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2604.23602