Cover Image

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Abdollahi, Armin, Ashrafi, Negin, Kamal, Mehdi, Pedram, Massoud
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Machine Learning
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalation
by: Abdollahi, Armin, et al.
Published: (2026)

MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications
by: Abdollahi, Armin, et al.
Published: (2024)

IC-D2S: A Hybrid Ising-Classical-Machines Data-Driven QUBO Solver Method
by: Abdollahi, Armin, et al.
Published: (2025)

Dynamic Co-Optimization Compiler: Leveraging Multi-Agent Reinforcement Learning for Enhanced DNN Accelerator Performance
by: Fayyazi, Arya, et al.
Published: (2024)

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
by: Calzada, Paul E., et al.
Published: (2025)

MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation
by: Zhang, Yongan, et al.
Published: (2024)

SAIM: Scalable Analog Ising Machine for Solving Quadratic Binary Optimization Problems
by: Razmkhah, Sasan, et al.
Published: (2024)

Exploring the Agentic Frontier of Verilog Code Generation
by: Yubeaton, Patrick, et al.
Published: (2026)

LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models
by: Thorat, Kiran, et al.
Published: (2025)

PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling
by: Zhong, Ruizhe, et al.
Published: (2024)

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs
by: Jin, Pengwei, et al.
Published: (2025)

VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
by: Wang, Zeng, et al.
Published: (2025)

RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts
by: Abdollahi, Armin, et al.
Published: (2025)

HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
by: Tang, Jinwei, et al.
Published: (2024)

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
by: Tan, Yan, et al.
Published: (2026)

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
by: Wang, Zeng, et al.
Published: (2025)

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
by: Pinckney, Nathaniel, et al.
Published: (2025)

Speculative Decoding for Verilog: Speed and Quality, All in One
by: Xu, Changran, et al.
Published: (2025)

CHOSEN: Compilation to Hardware Optimization Stack for Efficient Vision Transformer Inference
by: Sadeghi, Mohammad Erfan, et al.
Published: (2024)

RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning
by: Zhang, Xinyu, et al.
Published: (2026)

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
by: Zhang, Yang, et al.
Published: (2025)

DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model
by: Liu, Yi, et al.
Published: (2025)

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
by: Zhu, Yaoyu, et al.
Published: (2025)

NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions
by: Fayyazi, Arash, et al.
Published: (2023)

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation
by: Hong, Charles, et al.
Published: (2025)

VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
by: Nadimi, Bardia, et al.
Published: (2025)

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)

IR-Aware ECO Timing Optimization Using Reinforcement Learning
by: Jiang, Wenjing, et al.
Published: (2024)

HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
by: Abi-Karam, Stefan, et al.
Published: (2024)

Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification
by: Ikeda, Sosei, et al.
Published: (2025)

LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
by: Fang, Zhigang, et al.
Published: (2025)

Cross-Layer Co-Optimized LSTM Accelerator for Real-Time Gait Analysis
by: Ahmadilivani, Mohammad Hasan, et al.
Published: (2026)

Efficient FPGA Implementation of Time-Domain Popcount for Low-Complexity Machine Learning
by: Duan, Shengyu, et al.
Published: (2025)

Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations
by: Ahmed, Soyed Tuhin, et al.
Published: (2024)

NeuroScalar: A Deep Learning Framework for Fast, Accurate, and In-the-Wild Cycle-Level Performance Prediction
by: Wadle, Shayne, et al.
Published: (2025)

Reconfigurable Computing Challenge: Real-Time Graph Neural Networks for Online Event Selection in Big Science
by: Neu, Marc, et al.
Published: (2026)

The Cost of Dynamic Reasoning: Demystifying AI Agents and Test-Time Scaling from an AI Infrastructure Perspective
by: Kim, Jiin, et al.
Published: (2025)

Bespoke Co-processor for Energy-Efficient Health Monitoring on RISC-V-based Flexible Wearables
by: Vergos, Theofanis, et al.
Published: (2025)

MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration
by: Que, Zhiqiang, et al.
Published: (2025)

QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design
by: Huang, Lei, et al.
Published: (2025)